ADV3002-EVALZ AD [Analog Devices], ADV3002-EVALZ Datasheet

ADV3002-EVALZ

Manufacturer Part Number

ADV3002-EVALZ

Description

4:1 HDMI/DVI Switch with Equalization, DDC/CEC Buffers and EDID Replication

Manufacturer

AD [Analog Devices]

Datasheet

1.ADV3002-EVALZ.pdf (28 pages)

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

FEATURES

4 inputs, 1 output HDMI/DVI links

±8 kV ESD protection on input pins

HDMI 1.3a receive and transmit compliant

Bidirectional DDC buffers (SDA and SCL)

EDID replication reduces component count, while enabling

5 V combiner provides power to EDID replicator and CEC

Bidirectional buffered CEC line with integrated pull-up

Hot plug detect pulse low on channel switch with

Standards compatible: HDMI, DVI, HDCP, I

80-lead, 14 mm × 14 mm LQFP RoHS-compliant package

APPLICATIONS

Advanced television (HDTV) sets

Projectors

A/V receivers

Set-top boxes

GENERAL DESCRIPTION

The ADV3002 is a complete HDMI™/DVI link switch featuring

equalized transition minimized differential signaling (TMDS)

inputs, ideal for systems with long cable runs. The ADV3002

includes bidirectional buffering for the DDC bus and CEC line,

with integrated pull-up resistors for the CEC line. Additionally,

the ADV3002 includes an EDID replication function that enables

one EDID EEPROM to be shared for all four HDMI ports.

The ADV3002 is provided in a space-saving, 80-lead LQFP

surface-mount Pb-free plastic package and is specified to

operate over the 0°C to 85°C temperature range.

Supports 250 Mbps to 2.25 Gbps data rates and beyond

Supports 25 MHz to 225 MHz pixel clocks and beyond

Fully buffered unidirectional inputs/outputs

Switchable 50 Ω on-chip input terminations with manual

Equalized inputs with low added jitter compensate for

Loss of signal (LOS) detect circuit on TMDS clock

Output disable feature for reduced power dissipation

simultaneous access to all HDMI sources

buffer when local system power is off

resistors (26 kΩ)

programmable pulse width or direct manual control

or automatic control on channel switch

more than 20 meters of HDMI cable at 2.25 Gbps

4:1 HDMI/DVI Switch with Equalization,

DDC/CEC Buffers and EDID Replication

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

PRODUCT HIGHLIGHTS

I2C_ADDR[1:0]

IN_x_DATA2+

IN_x_DATA2–

IN_x_DATA1+

IN_x_DATA1–

IN_x_DATA0+

IN_x_DATA0–

DDC_xxx_A

DDC_xxx_B

DDC_xxx_C

DDC_xxx_D

IN_x_CLK+

IN_x_CLK–

I2C_SDA

I2C_SCL

CEC_IN

Input cable equalizer enables use of long cables at the

input. For a 24 AWG cable, the ADV3002 compensates for

more than 20 m at data rates up to 2.25 Gbps.

Auxiliary multiplexer isolates and buffers the DDC bus and

the CEC line, increasing total system capacitance limit.

EDID replication eliminates the need for multiple EDID

EEPROMs. EDID can be loaded from a single external

EEPROM or from a system microcontroller.

5 V power combiner powers the EDID replicator and CEC

buffer when local system power is off.

Integrated hot plug detect pulse low on channel switch

with programmable pulse width or direct manual control.

HPD_A

HPD_B

HPD_C

HPD_D

P5V_A

P5V_B

P5V_C

P5V_D

AVCC

–

FUNCTIONAL BLOCK DIAGRAM

SERIAL

SEL[1:0] TX_EN

INTERFACE

CONFIG

DDC/CEC

LOS

TMDS

EDID

EDID EEPROM INTERFACE

SWITCH

3.3V

BIDIRECTIONAL

CORE

PARALLEL

Figure 1.

HOT PLUG DETECT

REPLICATOR

CONTROL

COMBINER

CONTROL

LOGIC

RESETB

HPD

SWITCH

CORE

3.3V

ADV3002

www.analog.com

–

AVCC

AVEE

AVCC

OUT_CLK+

OUT_CLK–

OUT_DATA2+

OUT_DATA2–

OUT_DATA1+

OUT_DATA1–

OUT_DATA0+

OUT_DATA0–

AVCC

DDC_SCL_COM,

DDC_SDA_COM

CEC_OUT

EDID_ENABLE

EDID_SCL,

EDID_SDA

AMUXVCC

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