ADV3002-EVALZ AD [Analog Devices], ADV3002-EVALZ Datasheet - Page 25

• Manufacturer Part Number: ADV3002-EVALZ
• Description: 4:1 HDMI/DVI Switch with Equalization, DDC/CEC Buffers and EDID Replication
• Manufacturer: AD [Analog Devices]

cause the data on the four different channels of a group to arrive
out of alignment with one another. A good practice is to match
the trace lengths for a given group of four channels to within
0.05 inches on FR4 material.
Minimizing intrapair and interpair skew becomes increasingly
important as data rates increase. Any introduced skew consti-
tutes a correspondingly larger fraction of a bit period at higher
data rates.
Though the ADV3002 features input equalization and output
preemphasis, minimizing the length of the TMDS traces is needed
to reduce overall system signal degradation. Commonly used
PCB material, such as FR4, is lossy at high frequencies; therefore,
long traces on the circuit board increase signal attenuation,
resulting in decreased signal swing and increased jitter through
intersymbol interference (ISI).
Controlling the Characteristic Impedance of a TMDS
Differential Pair
The characteristic impedance of a differential pair depends on
a number of variables, including the trace width, the distance
between the two traces, the height of the dielectric material
between the trace and the reference plane below it, and the
dielectric constant of the PCB binder material. To a lesser
extent, the characteristic impedance also depends upon the
trace thickness and the presence of solder mask. There are
many combinations that can produce the correct characteristic
impedance. Generally, working with the PCB fabricator is
required to obtain a set of parameters to produce the desired
results.
One consideration is how to guarantee a differential pair with
a differential impedance of 100 Ω over the entire length of the
trace. One technique to accomplish this is to change the width
of the traces in a differential pair based on how closely one trace
is coupled to the other. When the two traces of a differential pair
are close and strongly coupled, they should have a width that
produces a100 Ω differential impedance. When the traces split
apart to go into a connector, for example, and are no longer so
strongly coupled, the width of the traces need to be increased to
yield a differential impedance of 100 Ω in the new configuration.
Ground Current Return
In some applications, it can be necessary to invert the output
pin order of the ADV3002. This requires a designer to route the
TMDS traces on multiple layers of the PCB. When routing dif-
ferential pairs on multiple layers, it is necessary to also reroute
the corresponding reference plane to provide one continuous
ground current return path for the differential signals. Standard
plated through-hole vias are acceptable for both the TMDS
traces and the reference plane. An example of this is illustrated
in Figure 35.
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TMDS Terminations
The ADV3002 provides internal 50 Ω single-ended terminations
for all of its high speed inputs and outputs. It is not necessary to
include external termination resistors for the TMDS differential
pairs on the PCB.
The output termination resistors of the ADV3002 back terminate
the output TMDS transmission lines. These back terminations
act to absorb reflections from impedance discontinuities on the
output traces, improving the signal integrity of the output traces
and adding flexibility to how the output traces can be routed.
For example, interlayer vias can be used to route the ADV3002
TMDS outputs on multiple layers of the PCB without severely
degrading the quality of the output signal.
Auxiliary Control Signals
There are four single-ended control signals associated with each
source or sink in an HDMI/DVI application. These are hot plug
detect (HPD), consumer electronics control (CEC), and two
display data channel (DDC) lines. The two signals on the DDC
bus are SDA and SCL (serial data and serial clock, respectively).
The DDC and CEC signals are buffered and switched through
the ADV3002, and the HPD signal is pulsed low by the ADV3002.
These signals do not need to be routed with the same strict
considerations as the high speed TMDS signals.
In general, it is sufficient to route each auxiliary signal as a
single-ended trace. These signals are not sensitive to impedance
discontinuities, do not require a reference plane, and can be
routed on multiple layers of the PCB. However, it is best to
follow strict layout practices whenever possible to prevent the
PCB design from affecting the overall application. The specific
routing of the HPD, CEC, and DDC lines depends upon the
application in which the ADV3002 is being used.
For example, the maximum speed of signals present on the aux-
iliary lines are 100 kHz I
any layout that enables 100 kHz I
SILKSCREEN
LAYER 1: SIGNAL (MICROSTRIP)
PCB DIELECTRIC
LAYER 2: GND (REFERENCE PLANE)
PCB DIELECTRIC
LAYER 3: PWR
(REFERENCE PLANE)
PCB DIELECTRIC
LAYER 4: SIGNAL (MICROSTRIP)
SILKSCREEN
Figure 35. Example Routing of Reference Plane
2
C data on the DDC lines, therefore,
KEEP REFERENCE PLANE
ADJACENT TO SIGNAL ON ALL
LAYERS TO PROVIDE CONTINUOUS
GROUND CURRENT RETURN PATH.
2
THROUGH-HOLE VIAS
C to be passed over the DDC
ADV3002