ISD5116 WINBOND [Winbond], ISD5116 Datasheet - Page 33

• Manufacturer Part Number: ISD5116
• Description: Single-Chip Voice Record/Playback Device Up to 16-Minute Duration with Digital Storage Capability
• Manufacturer: WINBOND [Winbond]

INT (Interrupt)
INT is an open drain output pin. The ISD5116 interrupt pin goes LOW and stays LOW when an Overflow
(OVF) or End of Message (EOM) marker is detected. Each operation that ends in an EOM or OVF
generates an interrupt, including the message cueing cycles. The interrupt is cleared by a READ
STATUS instruction that will give a status byte out the SDA line.
XCLK (External Clock Input)
The external clock input for the ISD5116 product has an internal pull-down device. Normally, the ISD5116
is operated at one of four internal rates selected for its internal oscillator by the Sample Rate Select bits. If
greater precision is required, the device can be clocked through the XCLK pin at 4.096 MHz as described
in
Because the anti-aliasing and smoothing filters track the Sample Rate Select bits, one must, for optimum
performance, maintain the external clock at 4.096 MHz AND set the Sample Rate Configuration bits to
one of the four values to properly set the filters to the correct cutoff frequency as described in
on page 22. The duty cycle on the input clock is not critical, as the clock is immediately divided by two
internally. If the XCLK is not used, this input should be connected to V
A0, A1 (Address Pins)
These two pins are normally strapped for the desired address that the ISD5116 will have on the I
interface. If there are four of these devices on the bus, then each must be strapped differently in order to
allow the Master device to address them individually. The possible addresses range from 80h to 87h,
depending upon whether the device is being written to, or read from, by the host. The ISD5116 has a 7-
bit slave address of which only A0 and A1 are pin programmable. The eighth bit (LSB) is the R/W bit.
Thus, the address will be 1000 0xy0 or 1000 0xy1. (See the
October 2000
Sample Rate
t
t
t
RAC
RACL0
RACL1
Section 4.3
(Minutes)
Duration
8.73
10.9
13.1
17.5
on page 22.
Sample Rate
4.0 kHz
2.5µs
0.5µs
2.0µs
(kHz)
8.0
6.4
5.3
4.0
RAC Waveform During Digital Erase
External Clock Input Table
Required Clock
1
.
25 µsec
5.3 kHz
1.87µs
0.37µs
1.50µs
(kHz)
4096
4096
4096
4096
table in section 3.1.1
FLD1
0
0
1
1
SSD
6.4 kHz
1.56µs
0.31µs
1.25µs
.
.
25 µsec
FLD0
0
1
0
1
on page 9.)
Filter Knee (kHz)
8.0 kHz
1.25µs
0.25µs
1.00µs
3.4
2.7
2.3
1.7
Section 4.3
Page 32
2
C serial