ISD5116 WINBOND [Winbond], ISD5116 Datasheet - Page 37

• Manufacturer Part Number: ISD5116
• Description: Single-Chip Voice Record/Playback Device Up to 16-Minute Duration with Digital Storage Capability
• Manufacturer: WINBOND [Winbond]

6.3 POWER AND GROUND PINS
V
To minimize noise, the analog and digital circuits in the ISD5116 device use separate power busses.
These +3 V busses lead to separate pins. Tie the V
both supplies as near to the package as possible.
V
The ISD5116 series utilizes separate analog and digital ground busses. The analog ground (V
should be tied together as close to the package as possible and connected through a low-impedance
path to power supply ground. The digital ground (V
impedance path to power supply ground. These ground paths should be large enough to ensure that the
impedance between the V
to V
nected to V
NC (Not Connect)
These pins should not be connected to the board at any time. Connection of these pins to any signal,
ground or V
6.4 SAMPLE PC LAYOUT
The SOIC package is illustrated from the top. PC board traces and the three chip capacitors are on the
bottom side of the board.
October 2000
CCA
SSA
Note 3
SSD
, V
, V
SSD
CCD
Note 1: V
separated back to the V
point..
Note 2: V
separate back to the V
point.
Note 3: The Digital and Analog grounds
tie together at the power supply. The
V
filter capacitors per good engineering
practice (typ. 50 to 100 uF).
through the substrate resistance. In a chip-on-board design, the die attach area must be con-
CCA
(Ground Inputs)
(Voltage Inputs)
SSD
CC,
(Digital Ground)
and V
V
S
S
D
.
may result in incorrect device behavior or cause damage to the device.
SSD
CCD
CCD
traces should be kept
traces should be kept
supplies will also need
Note 1
SSA
pins and the V
CC
SS
Supply feed
supply feed
SSD
1
pin is less than 3 . The backside of the die is connected
O
O
O
O
O
O
O
O
O
O
O
O
O
O
SSD
Analog Ground
CCD
) pin should be connected through a separate low
C3
pins together as close as possible and decouple
C2
C1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
XCLK
V
SSA
Note 2
Note 3
C1=C2=C3=0.1 uF chip Capacitors
To
V
CCA
V
C
C
D
Page 36
SSA
) pins