ADL5519ACPZ-R2 AD [Analog Devices], ADL5519ACPZ-R2 Datasheet - Page 13

• Manufacturer Part Number: ADL5519ACPZ-R2
• Description: 1 MHz to 10 GHz, 50 dB Dual Log Detector/Controller
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
COMR
THEORY OF OPERATION
The ADL5519 is a dual-channel 6-stage demodulating
logarithmic amplifier, specifically designed for use in RF
measurement and power control applications at frequencies
up to 10 GHz. Sharing much of its design with the AD8317
logarithmic detector/controller, the ADL5519 maintains tight
intercept variability vs. temperature over a 50 dB range. Each
measurement channel offers equivalent performance to the
AD8317. The complete circuit block diagram is shown in
Figure 9.
COMR
PWDN
COMR
Each measurement channel is a fully differential design
and uses a proprietary, high speed SiGe process, extending
high frequency performance. Figure 10 shows the basic
diagram of the ADL5519’s channel A signal path, the
functionality is identical for channel B.
INHA
INLA
INHA
INHB
INLB
INLA
25
26
27
28
29
30
31
32
DET
Figure 10. Single Channel Block Diagram
24
1
Log Detector
Log Detector
CHANNEL B
CHANNEL A
DET
23
2
OUTB
OUTA
Figure 9. Block Diagram
22
3
BIAS
DET
21
4
TEMP
20
5
DET
19
6
18
7
V
I
17
8
V
I
25
26
27
28
29
30
31
32
NC
NC
OUTA
FBKA
OUTP
OUTN
FBKB
OUTB
VSTA
OUTA
CLPA
Rev. PrB | Page 13 of 27
The maximum input with ±1 dB log-conformance error is
typically 0 dBm (re: 50 Ω). The noise spectral density referred
to the input is 1.15 nV/√Hz, which is equivalent to a voltage of
118 μV rms in a 10.5 GHz bandwidth or a noise power of −66
dBm (re: 50 Ω). This noise spectral density sets the lower limit
of the dynamic range. However, the low end accuracy of the
ADL5519 is enhanced by specially shaping the demodulating
transfer characteristic to partially compensate for errors due to
internal noise. The common pin, COMR, provides a quality low
impedance connection to the printed circuit board (PCB) ground.
The package paddle, which is internally connected to the
COMR pin, should also be grounded to the PCB to reduce
thermal impedance from the die to the PCB.
The logarithmic function is approximated in a piecewise
fashion by six cascaded gain stages. (For a more comprehensive
explanation of the logarithm approximation, please refer to the
AD8307 data sheet, available at www.analog.com.) The cells
have a nominal voltage gain of 9 dB each and a 3 dB bandwidth
of 10.5 GHz. Using precision biasing, the gain is stabilized over
temperature and supply variations. The overall dc gain is high,
due to the cascaded nature of the gain stages. An offset
compensation loop is included to correct for offsets within the
cascaded cells. At the output of each of the gain stages, a square-
law detector cell is used to rectify the signal.
The RF signal voltages are converted to a fluctuating differential
current having an average value that increases with signal level.
Along with the six gain stages and detector cells, an additional
detector is included at the input of each measurement channel,,
providing a 50 dB dynamic range in total. After the detector
currents are summed and filtered, the following function is
formed at the summing node:
where:
I
V
V
the output voltage would be 0 V, if it were capable of going to 0 V).
D
IN
INTERCEPT
is the internally set detector current.
I
is the input signal voltage.
D
× log
is the intercept voltage (that is, when V
10
(V
IN
/V
INTERCEPT
)
IN
= V
INTERCEPT
ADL5519
,