ADL5519ACPZ-R2 AD [Analog Devices], ADL5519ACPZ-R2 Datasheet - Page 15

• Manufacturer Part Number: ADL5519ACPZ-R2
• Description: 1 MHz to 10 GHz, 50 dB Dual Log Detector/Controller
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
POWER-DOWN INTERFACE
The operating and stand-by currents for the ADL5519 at
25°C are approximately 65 mA and 1 mA, respectively. The
PWDN and ADJ[A,B] pins are connected to the base of
and NPN transistor to force a power down condition.
Typically, when PWDN is pulled >2.5 V, the ADL5519 is
powered down from 65mA to <1mA. The output reaches
to within 0.1 dB of its steady-state value in about 1.6 μs; the
reference voltage is available to full accuracy in a much
shorter time. This wake-up response time varies depending
on the input coupling network and the capacitance at pins
CLP[A, B].
The individual log channels can be disabled by installing a
0Ω pull up resistor from ADJ[A,B] to VPS[A,B].
SETPOINT INTERFACE, VST[A, B]
The V
an internal op amp. The V
internal 1.5 kΩ resistor to generate I
V
If V
The result is
The slope is given by –I
example, if a resistor divider to ground is used to generate a
V
V/decade or −44 mV/dB.
OUTPUT INTERFACE, OUT[A, B]
The OUT[A,B] pin is driven by a PNP output stage. An
internal 10 Ω resistor is placed in series with the output and
the OUT[A,B] pin. The rise time of the output is limited
mainly by the slew on CLP[A,B]. The fall time is an RC-
limited slew given by the load capacitance and the pull-
down resistance at OUT[A,B]. There is an internal pull-
down resistor of 1.6 kΩ. A resistive load at OUT[A,B] is
placed in parallel with the internal pull-down resistor to
provide additional discharge current.
OUT
SET
SET
−I
V
voltage of V
is applied to VSET, the feedback loop forces
SET
OUT
= V
D
× log
Figure 14. VST[A, B] Interface Simplified Schematic
input drives the high impedance (20 kΩ) input of
= (−I
OUT
VSET
/2x, then I
10
(V
D
OUT
× 1.5 kΩ × 2x) × log
IN
/V
/2, then x = 2. The slope is set to −880
20kΩ
INTERCEPT
D
20kΩ
SET
× 2x × 1.5 kΩ = −22 mV/dB × x. For
COMM
SET
V
= V
SET
) = I
voltage appears across the
OUT
/(2x × 1.5 kΩ).
SET
SET
.
1.5kΩ
. When a portion of
10
(V
COMM
IN
/V
I
SET
INTERCEPT
)
Rev. PrB | Page 15 of 27
OUT[A, B] can source and sink up to 2.2 mA.
DIFFERENCE OUTPUT, OUT[P, N]
The ADL5519 incorporates two operational amplifiers with
rail-to-rail output capability to provide a channel difference
output.
As in the case of the output drivers for OUT[A, B], the output
stages have the capability of driving 2.2 mA. OUTA and OUTB
are internally connected through 1 kΩ resistors to the inputs of
each op amp. The pin VLVL is connected to the positive terminal
of both op amps through 1 kΩ resistors to provide level shifting.
The negative feedback terminal is also made available through a
1 kΩ resistor. The input impedance of VLVL is 1 kΩ and
FBK[A, B] is 2 kΩ. See Figure 17 for the connections of these
pins.
If OUTP is connected to FBKA, then OUTP is given as
If OUTN is connected to FBKB, then OUTN is given as
OUTP = OUTA – OUTB + VLVL
OUTN = OUTB – OUTA + VLVL
Figure 17. Op Amp Connections (All Resistors are 1 kΩ ± 20%)
OUTA
OUTB
Figure 15. OUT[A, B] Interface Simplified Schematic
Figure 16. OUT[P, N] Interface Simplified Schematic
CLP[A,B]
OUTB
OUTB
OUTA
OUTA
1kΩ
1kΩ
1kΩ
1kΩ
VPS[A, B]
FBKA COMR
FBKB COMR
VLVL
VLVL
1kΩ
1kΩ
1kΩ
1kΩ
COMR
VPSR
VPSR
1.2kΩ
400Ω
OUTP
OUTN
OUT[A, B]
27
28
29
30
(10)
(9)
FBK
OUT
OUT
FBK
A
B
P
N
ADL5519