ADL5519ACPZ-R2 AD [Analog Devices], ADL5519ACPZ-R2 Datasheet - Page 18

• Manufacturer Part Number: ADL5519ACPZ-R2
• Description: 1 MHz to 10 GHz, 50 dB Dual Log Detector/Controller
• Manufacturer: AD [Analog Devices]

ADL5519
and OUTP. This changes the output equation for OUTB and
OUTP to
For VLVL < OUTA/2,
Otherwise,
The previous equations are valid when Channel A is driven and
Channel B is slaved through a feedback loop. When Channel B
is driven and Channel A is slaved, the above equations can be
altered by changing OUTB to OUTA and OUTN to OUTP.
Automatic Power Control
Figure 20 shows how the device should be reconfigured to
control output power.
The RF input to the device is configured as before. A directional
coupler taps off some of the power being generated by the VGA
(typically a 10 dB to 20 dB coupler is used). A power splitter can
be used instead of a directional coupler if there are no concerns
about reflected energy from the next stage in the signal chain.
Some additional attenuation may be required to set the
maximum input signal at the ADL5519 to be equal to the
recommended maximum input level for optimum linearity and
temperature stability at the frequency of operation.
VSTA and OUTA are no longer shorted together. OUTA now
provides a bias or gain control voltage to the VGA. The gain
control sense of the VGA must be positive and monotonic, that
is, increasing voltage tends to increase gain. However, the gain
control transfer function of the device does not need to be well
controlled or particularly linear. If the gain control sense of the
VGA is negative, an inverting op amp circuit with a dc offset
shift can be used between the ADL5519 and the VGA to keep
the gain control voltage in the 0 V to 5 V range.
VSTA becomes the setpoint input to the system. This can be
driven by a DAC, as shown in Figure 20, if the output power is
expected to vary, or it can simply be driven by a stable reference
voltage if constant output power is required. This DAC should
have an output swing that covers the 0 V to 3.5 V range. The
AD7391 and AD7393 serial-input and parallel-input 10-bit
DACs provide adequate resolution (4 mV/bit) and an output
swing up to 4.5 V.
When VSTA is set to a particular value, the ADL5519 compares
this value to the equivalent input power present at the RF input.
If these two values do not match, OUTA increases or decreases
in an effort to balance the system. The dominant pole of the
error amplifier/integrator circuit that drives OUTA is set by the
capacitance on Pin CLPA; some experimentation may be
necessary to choose the right value for this capacitor. In general,
OUTB = 2 × OUTA − VLVL
OUTN = 0 V
OUTN = 2 × VLVL – OUTA
(14)
(15)
(16)
Rev. PrB | Page 18 of 27
CLPA should be chosen to provide stable loop operation for the
complete output power control range. If the slope (in dB/V) of
the gain control transfer function of the VGA is not constant,
CLPA must be chosen to guarantee a stable loop when the gain
control slope is at its maximum. On the other hand, CLPA must
provide adequate averaging to the internal low range squaring
detector so that the rms computation is valid. Larger values of
CLPA tend to make the loop less responsive.
The relationship between VSTA and the RF input follows from
the measurement mode behavior of the device. For example,
from Figure 8, which shows the measurement mode transfer
function at 880 MHz, it can be seen that an input power of
−10 dBm yields an output voltage of 2.5 V. Therefore, in
controller mode, VSTA should be set to 2.5 V, which results in
an input power of −10 dBm to the ADL5519.
Automatic Gain Control
Figure 21 shows how the ADL5519 can be connected to provide
automatic gain control to an amplifier or signal chain.
Additional pins are omitted for clarity. In this configuration,
both log detectors are connected in measurement mode with
appropriate filtering being used on CLP[A, B]. OUTA, however,
is also connected to the VLVL pin of the on-board difference
amplifier. Also, the OUTP output of the difference amplifier
drives a variable gain element (either VVA or VGA) and is
connected back to the FBKA input via a capacitor so that it is
operating as an integrator.
Assume that OUTA is much bigger than OUTB. Because OUTA
also drives VLVL, this voltage is also present on the noninverting
input of the op amp driving OUTP. This results in a net current
flow from OUTP through the integrating capacitor into the
FBKA input. This results in the voltage on OUTP decreasing. If
the gain control transfer function of the VVA/VGA is negative,
this increases the gain, which in turn increases the input signal
to INHB. The output voltage on the integrator continues to
P
IN
DAC
Figure 20. Operation in Controller Mode for Automatic Power Control
V
(OUTPUT POWER
APC
INCREASES AS
0V TO 3.5V
VGA OR VVA
VSTA
ADL5519
DECREASES)
OUTA
V
APC
(0V TO 4.9V AVAILABLE SWING)
CLPA
INHA
INLA
Preliminary Technical Data
SEE TEXT
0.1μF
0.1μF
50Ω
ATTENUATOR
P
OUT