CS8416-IZ CIRRUS [Cirrus Logic], CS8416-IZ Datasheet - Page 8

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CS8416-IZ

Manufacturer Part Number
CS8416-IZ
Description
192 kHZ DIGITAL AUDIO INTERFACE RECEIVER
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(T
Inputs: Logic 0 = 0 V, Logic 1 = VL+; C
Notes: 9. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is
8
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
A
= 25 °C for suffixes ‘CS’ &’CZ’, T
10. Data must be held for sufficient time to bridge the transition time of CCLK.
11. For f
dictated by the timing requirements necessary to access the Channel Status memory. Access to the
control register file can be carried out at the full 6 MHz rate. The minimum allowable input sample rate
is 32 kHz, so choosing CCLK to be less than or equal to 4.1 MHz should be safe for all possible
conditions.
sck
<1 MHz.
Parameter
CDOUT
CDIN
CCLK
CS
t css
A
= -40 to 85°C for ‘IS’ & ‘IZ’ ; VA+ = VD+ = 3.3 V ± 5%, VL+ = 3.135 to 5.5V,
t r2
L
= 20 pF)
Figure 3. SPI Mode Timing
t dsu
t scl
t f2
(Note
(Note
(Note
(Note
t sch
t dh
10)
11)
11)
9)
t pd
Symbol
t
t
f
t
t
t
t
t
sck
csh
css
sch
dsu
t
t
t
t
scl
dh
pd
r1
r2
r2
f1
Min
1.0
20
66
66
40
15
t csh
0
-
-
-
-
-
Max
100
100
6.0
50
25
25
-
-
-
-
-
-
CS8416
DS578PP2
MHz
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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