CS8420 CIRRUS [Cirrus Logic], CS8420 Datasheet - Page 64

• Manufacturer Part Number: CS8420
• Description: DIGITAL AUDIO SAMPLE RATE CONVERTER
• Manufacturer: CIRRUS [Cirrus Logic]

14.6 Hardware Mode 5 Description
Hardware Mode 5 data flow is shown in Figure 30.
Audio data is input via the AES3 receiver, and rout-
ed to the serial audio output port. The PRO, COPY,
ORIG, EMPH, and AUDIO channel status bits are
output on pins. The decoded C and U bits are also
output, clocked by both edges of OLRCK (master
mode only, see Figure 21).
If a validity, parity, bi-phase or lock receiver error
occurs, the current audio sample is passed unmod-
ified to the serial audio output port.
64
(AES3 Receiver Only)
RXP
RXN
RMCK
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT)
are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
AES3 Rx
&
Decoder
VD+
DFC0
RERR
Figure 30. Hardware Mode 5 - AES3 Receiver Only
VD+
NVERR
DFC1
CHS
S/AES
COPY ORIG EMPH
C & U bit Data Buffer
VD+
H/S
Start-up options are shown in Table 12, and allow
choice of the serial audio output port as a master or
slave, and the serial audio port format. The follow-
ing pages contain the detailed pin descriptions for
hardware mode 5.
SDOUT ORIG EMPH
LO
HI
-
-
-
-
Table 12. Hardware Mode 5 Start-up Options
PRO AUDIO
LO
LO
HI
HI
-
-
LO
LO
HI
HI
-
-
Serial
Audio
Output
RCBL
Serial Output Port is Slave
Serial Output Port is Master
Serial Output Format OF1
Serial Output Format OF2
Serial Output Format OF3
Serial Output Format OF5
OMCK
C
U
OLRCK
OSCLK
SDOUT
Function
CS8420
DS245PP2