CS8420 CIRRUS [Cirrus Logic], CS8420 Datasheet - Page 65

• Manufacturer Part Number: CS8420
• Description: DIGITAL AUDIO SAMPLE RATE CONVERTER
• Manufacturer: CIRRUS [Cirrus Logic]

14.6.1 Pin Description - Hardware Mode 5
Overall Device Control:
DFC0, DFC1 - Data Flow Control Inputs
S/AES - Serial Audio or AES3 Input Select
OMCK - Output Section Master Clock Input
Audio Output Interface:
SDOUT - Serial Audio Output Port Data Output
OSCLK - Serial Audio Output Port Bit Clock Input or Output
OLRCK - Serial Audio Output Port Left/Right Clock Input or Output
AES3/SPDIF Receiver Interface:
RXP, RXN - Differential Line Receiver Inputs
RMCK - Input Section Recovered Master Clock Output
DS245PP2
DFC0 and DFC1 inputs determine the major data flow options available in hardware mode, according to
Table 3.
S/AES is connected to DGND in hardware mode 5, in order to select the AES3 input.
Output section master clock input. This pin is not used in this mode and should be connected to DGND.
Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down
resistor.
Serial bit clock for audio data on the SDOUT pin.
Word rate clock for the audio data on the SDOUT pin. The frequency will be at the input sample rate
(Fsi).
Differential line receiver inputs, carrying AES3 type data.
Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi).
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