ST16C1450CJ28 EXAR [Exar Corporation], ST16C1450CJ28 Datasheet - Page 15

• Manufacturer Part Number: ST16C1450CJ28
• Description: 2.97V TO 5.5V UART
• Manufacturer: EXAR [Exar Corporation]

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REV. 4.2.0
See “Receiver” on page 10.
See “Transmitter” on page 9.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the THR is empty. If the THR is empty
when this bit is enabled, an interrupt will be generated. Note that this interrupt does not behave in the same
manner as the industry standard 16C550.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in the RHR.
IER[3]: Modem Status Interrupt Enable
IER[4]: Reserved
IER[5]: Special Mode Enable
IER[7:6]: Reserved
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table,
associated with each of these interrupt levels.
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
4.4
Logic 0 = Disable the receive data ready interrupt (default).
Logic 1 = Enable the receiver data ready interrupt.
Logic 0 = Disable Transmit Ready interrupt (default).
Logic 1 = Enable Transmit Ready interrupt.
Logic 0 = Disable the receiver line status interrupt (default).
Logic 1 = Enable the receiver line status interrupt.
Logic 0 = Disable the modem status register interrupt (default).
Logic 1 = Enable the modem status register interrupt.
Logic 0 = Disable special mode functions (default).
Logic 1 = Enable special mode functions in addition to basic ST16C1450 functions. Enables ISR bits 4-5
(TXRDY/RXRDY), MCR bit-2 (soft reset) and MCR bit-7 (power down) functions.
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
Interrupt Enable Register (IER) - Read/Write
Interrupt Status Register (ISR) - Read-Only
Table
4, shows the data values (bits 0-3) for the interrupt priority levels and the interrupt sources
See “Interrupt Clearing:” on page 16.
15
2.97V TO 5.5V UART
ST16C1450/51