X28HC256DI-12 INTERSIL [Intersil Corporation], X28HC256DI-12 Datasheet - Page 4

• Manufacturer Part Number: X28HC256DI-12
• Description: 5 Volt, Byte Alterable EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

PIN CONFIGURATION
PIN DESCRIPTIONS
Addresses (A
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all
read/write operations. When CE is HIGH, power con-
sumption is reduced.
Output Enable (OE)
The Output Enable input controls the data output buff-
ers, and is used to initiate read operations.
Data In/Data Out (I/O
Data is written to or read from the X28HC256 through
the I/O pins.
V
A
A
I/O
I/O
I/O
SS
A
A
A
A
A
A
A
A
14
12
7
6
5
4
3
2
1
0
0
1
2
FLAT PLASTIC
PLASTIC DIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
X28HC256
CERDIP
SOIC
0
-A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
)
0
V
WE
A
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
-I/O
CC
13
8
9
11
10
7
6
5
4
3
7
4
)
I/O
NC
A
A
A
A
A
A
A
6
5
4
3
2
1
0
0
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
4
X28HC256
3
X28HC256
(Top View)
2
PLCC
LCC
1 32 31 30
Write Enable (WE)
The Write Enable input controls the writing of data to
the X28HC256.
PIN NAMES
29
28
27
26
25
24
23
22
21
I/O
Symbol
A
V
0
V
WE
CE
OE
NC
0
A
A
A
NC
OE
A
CE
I/O
I/O
-A
CC
SS
-I/O
8
9
11
10
7
6
14
7
Data Input/Output
Address Inputs
Output Enable
12
11
9
7
5
4
Description
Write Enable
Chip Enable
I/O
I/O
A
A
A
A
No Connect
1
3
5
6
1
0
Ground
13
10
+5V
8
6
2
3
I/O
A
A
A
A
A
(Bottom View)
12
7
0
2
4
X28HC256
2
15
14
28
PGA
1
I/O
V
V
A
SS
CC
14
3
17
16
20
22
24
27
I/O
I/O
CE
OE
A
WE
9
5
4
May 17, 2006
18
19
21
23
25
26
FN8108.1
I/O
I/O
A
A
A
A
10
11
8
13
6
7