X28HC256DI-12 INTERSIL [Intersil Corporation], X28HC256DI-12 Datasheet - Page 8

• Manufacturer Part Number: X28HC256DI-12
• Description: 5 Volt, Byte Alterable EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific
addresses. Refer to Figure 6 and 7 for the sequence.
SOFTWARE DATA PROTECTION
Figure 6. Timing Sequence—Byte or Page Write
Figure 7. Write Sequence for Software Data
Protection
V
CC
WE
CE
0V
Re-Enters Data
Protected State
Write Data A0
Write Data AA
Write Data 55
Write Data XX
Last Address
to Address
to Address
to Address
Write Last
Data
Address
After t
Address
Byte to
to Any
2AAA
5555
5555
WC
8
5555
AAA
Byte/Page
Load Enabled
Optional
Byte/Page
Load Operation
2AAA
55
5555
A0
X28HC256
≤ t
BLC MAX
The three-byte sequence opens the page write window,
enabling the host to write from one to one hundred
twenty-eight bytes of data. Once the page load cycle
has been completed, the device will automatically be
returned to the data protected state.
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used and data has been written, the
X28HC256 will automatically disable further writes
unless another command is issued to cancel it. If no
further commands are issued the X28HC256 will be
write protected during power-down and after any sub-
sequent power-up.
Note: Once initiated, the sequence of write operations
should not be interrupted.
Writes
Byte
Age
ok
or
t
WC
Write
Protected
(V
CC
)
May 17, 2006
FN8108.1