X28HC256DI-12 INTERSIL [Intersil Corporation], X28HC256DI-12 Datasheet - Page 7

• Manufacturer Part Number: X28HC256DI-12
• Description: 5 Volt, Byte Alterable EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

THE TOGGLE BIT I/O
Figure 4. Toggle Bit Bus Sequence
Figure 5. Toggle Bit Software Flow
¬
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to implement
DATA Polling. This can be especially helpful in an
array comprised of multiple X28HC256 memories that
is frequently updated. The timing diagram in Figure 4
illustrates the sequence of events on the bus. The
software flow diagram in Figure 5 illustrates a method
for polling the Toggle Bit.
I/O
WE
CE
OE
6
Last
Write
Load Accum
From Addr n
Last Write
Accum with
X28C256
Compare
Compare
Ready
Addr n
ok?
Yes
Yes
6
*
7
No
V
OH
* I/O
6
Beginning and ending state of I/O
V
OL
X28HC256
HIGH Z
HARDWARE DATA PROTECTION
The X28HC256 provides two hardware features that
protect nonvolatile data from inadvertent writes.
– Default V
– Write Inhibit—Holding either OE LOW, WE HIGH, or
SOFTWARE DATA PROTECTION
The X28HC256 offers a software-controlled data pro-
tection feature. The X28HC256 is shipped from Intersil
with the software data protection NOT ENABLED; that
is, the device will be in the standard operating mode.
In this mode data should be protected during power-
up/down operations through the use of external cir-
cuits. The host would then have open read and write
access of the device once V
The X28HC256 can be automatically protected during
power-up and power-down (without the need for exter-
nal circuits) by employing the software data protection
feature. The internal software data protection circuit is
enabled after the first write operation, utilizing the soft-
ware algorithm. This circuit is nonvolatile, and will
remain set for the life of the device unless the reset
command is issued.
Once the software protection is enabled, the X28HC256 is
also protected from inadvertent and accidental writes in
the powered-up state. That is, the software algorithm must
be issued prior to writing additional data to the device.
when V
CE HIGH will prevent an inadvertent write cycle during
power-up and power-down, maintaining data integrity.
6
will vary.
CC
CC
is 3.5V typically.
*
Sense—All write functions are inhibited
CC
was stable.
X28C512/513
Ready
May 17, 2006
FN8108.1