X28HC64DI-12 INTERSIL [Intersil Corporation], X28HC64DI-12 Datasheet - Page 14

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X28HC64DI-12

Manufacturer Part Number
X28HC64DI-12
Description
5 Volt, Byte Alterable EEPROM
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet

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CE CONTROLLED WRITE CYCLE
Page Write Cycle
Notes: (7) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH
Address*
Data Out
Address
Data In
(8) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to
OE
WE
OE
CE
WE
CE
to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a
polling operation.
either the CE or WE controlled write cycle timing.
I/O
(7)
(8)
*For each successive write within the page write operation, A
writes to an unknown address could occur.
t
WP
t
OES
14
t
AS
Byte 0
t
CS
t
DV
t
WPH
Byte 1
t
AH
t
BLC
t
CW
X28HC64
HIGH Z
Byte 2
t
DS
Data Valid
t
OEH
Byte n
t
WC
6
t
t
–A
CH
DH
12
should be the same or
Byte n+1
Last Byte
Byte n+2
t
WC
June 1, 2005
FN8109.0

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