AT29C432-12TC ATMEL [ATMEL Corporation], AT29C432-12TC Datasheet - Page 2

• Manufacturer Part Number: AT29C432-12TC
• Description: 4 Megabit 5-volt Flash with 256K E2PROM Memory
• Manufacturer: ATMEL [ATMEL Corporation]

Device Operation
READ: The Flash memory array is read like a Static
RAM. When CEF and OE are low, and WE and CEE are
high, the data stored at the memory location determined
by the address inputs is asserted on the I/O’s.
PROGRAM: The Flash memory array is divided into 2048
sectors, each comprised of 256 bytes. For read opera-
tions these sectors appear seamless; however, for repro-
gramming the sector boundaries must be taken into ac-
count. The state of adresses A0 - A3 and A15 - A18 spec-
ify the individual byte address within a sector and the state
of addresses A4 - A14 define the sector to be written.
The AT29C432 employs the JEDEC standard software
data protection feature; therefore, each programming se-
quence must be preceded by the three byte program com-
mand sequence. Using the software data protection fea-
ture, byte loads are used to enter the 256 bytes of a sector
to be programmed. The Flash memory array can only be
programmed using the software data protection feature.
The Flash memory array is programmed on a sector basis.
If a byte of data within the sector is to be changed, data for
the entire 256-byte sector must be loaded into the device.
The Flash memory array automatically does a sector
erase prior to loading the data into the sector. An erase
command is not required.
Software data protection protects the device from inadver-
tent programming. A series of three program commands
to specific addresses with specific data must be presented
to the device before programming may occur. The same
2
Flash Memory Array
AT29C432
three program commands must begin each program op-
eration. All software program commands must obey the
sector program timing specifications. Power transitions
will not reset the software data protection feature, however
the software feature will guard against inadvertent pro-
gram cycles during power transitions.
Any attempt to write to the device without the three-byte
command sequence will start the internal write timers. No
data will be written to the device; however, for the duration
of t
tion.
After the software data protection’s three-byte command
code is given, a byte load is performed by applying a low
pulse on the WE or CEF input with CEF or WE low (re-
spectively) and OE and CEE high. The address is latched
on the falling edge of CEF or WE, whichever occurs last.
The data is latched by the first rising edge of CEF or WE.
The 256 bytes of data must be loaded into each sector.
Any byte that is not loaded during the programming of its
sector will be indeterminate. Once the bytes of a sector
are loaded into the device, they are simultaneously pro-
grammed during the internal programming period. After
the first data byte has been loaded into the device, suc-
cessive bytes are entered in the same manner. Each new
byte to be programmed must have its high to low transition
on WE (or CEF) within 150 s of the low to high transition
of WE (or CEF) of the preceding byte. If a high to low
transition is not detected within 150 s of the last low to
WCF
, a read operation will effectively be a polling opera-
(continued)