AT29C432-12TC ATMEL [ATMEL Corporation], AT29C432-12TC Datasheet - Page 3

• Manufacturer Part Number: AT29C432-12TC
• Description: 4 Megabit 5-volt Flash with 256K E2PROM Memory
• Manufacturer: ATMEL [ATMEL Corporation]

Device Operation (Continued)
high transition, the load period will end and the internal
programming period will start. The sector address must
be valid during each high to low transition of WE (or CEF).
The bytes may be loaded in any order; sequential loading
is not required. Once a programming operation has been
initiated, and for the duration of t
effectively be a data polling operation.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the Flash memory
array in the following ways: (a) V
low 3.8V (typical), the program function is inhibited. (b)
V
sense level, the device will automatically time out 10 ms
(typical) before programming. (c) Program inhibit—hold-
ing any one of OE low, CEF high or WE high inhibits pro-
gram cycles. (d) Noise filter—pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
DATA POLLING: A maximum amount of time for pro-
gram and write operations is specified; the actual time is
frequently faster than the specification. In order to take ad-
vantage of the faster typical times, the Flash memory ar-
ray features DATA polling to indicate the end of a program
cycle. During a program cycle an attempted read of the
last byte loaded will result in the complement of the loaded
data on I/O7. Once the program cycle has been com-
pleted, true data is valid on all outputs and the next cycle
may begin. DATA polling may begin at any time during the
program cycle.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product. In addition, users may wish to use the
software product identification mode to identify the part
(i.e. using the device code), and have the system software
use the appropriate sector size for program operations.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
READ: The E
RAM. When CEE and OE are low and WE and CEF are
high, the data stored at the memory location determined
by the address inputs is asserted on the I/O’s.
WRITE: The E
either a single byte write or page write operation. Be-
cause software data protection is always enabled both
write operations must be preceded by the three byte write
CC
power on delay—once V
E
2
PROM Memory Array
2
PROM memory array is read like a Static
2
PROM memory array may be written in
CC
WCF
CC
has reached the V
, a read operation will
sense—if V
CC
is be-
CC
command sequence. This sequence should then immedi-
ately be followed by one to sixteen bytes of data. After the
last byte has been written, the AT29C432 will automat-
ically time itself to completion of the internal write cycle.
The write cycle is initiated by both WE and CEE going low;
the address is latched by the falling edge of WE or CEE
(whichever occurs last) and the data is latched by the ris-
ing edge of WE or CEE (whichever occurs first). All write
operations (byte or page) must conform to the page write
limits as shown in the timing diagram for E
operations. All bytes during a page write operation must
reside on the same page as defined by the state of the A4
- A14 inputs. For each WE high to low transition during
the page write operation, A4 - A14 must be the same.
The A0 - A3 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in
any order and may be altered within the same load period.
Only bytes which are specified for writing will be written;
unnecessary cycling of other bytes within the page does
not occur.
During the internal write operation (t
the E
tions; however, attempts to read the Flash array will return
valid data.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the E
memory array in the following ways: (a) V
V
ited. (b) V
V
ms (typical) before programming. (c) Program inhibit—
holding any one of OE low, CEE high or WE high inhibits
program cycles. (d) Noise filter—pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
DATA POLLING: A maximum amount of time for pro-
gram and write operations is specified; the actual time is
frequently faster than the specification. In order to take
advantage of the faster typical times, the E
ory array features DATA polling to indicate the end of a
program cycle. During a program cycle an attempted read
of the last byte loaded will result in the complement of the
loaded data on I/O7. Once the program cycle has been
completed, true data is valid on all outputs and the next
cycle may begin. DATA polling may begin at any time dur-
ing the program cycle.
CC
CC
is below 3.8V (typical), the program function is inhib-
sense level, the device will automatically time out 10
2
PROM will be equivalent to DATA polling opera-
CC
power on delay—once V
AT29C432
WCE
CC
) attempts to read
has reached the
2
2
PROM mem-
CC
(continued)
PROM write
sense—if
2
PROM
3