ADP2116-EVALZ AD [Analog Devices], ADP2116-EVALZ Datasheet - Page 27

• Manufacturer Part Number: ADP2116-EVALZ
• Description: Configurable, Dual 3 A/Single 6 A, Synchronous, Step-Down DC-to-DC Regulator
• Manufacturer: AD [Analog Devices]

To avoid saturation, the rated current of the inductor must be
larger than the maximum peak inductor current, I
where:
I
ΔI
The ADP2116 can be configured in either a 3 A/3 A or 3 A/2 A
current-limit configuration; therefore, the current-limit
thresholds for the two channels are different in each setting.
The inductor chosen for each channel must have at least the
peak output current limit of the IC in each case for robust
operation during short-circuit conditions. The following
inductors are recommended:
•
•
OUTPUT CAPACITOR SELECTION
The output capacitor selection affects both the output voltage
ripple and the loop dynamics of the converter. The ADP2116
is designed for operation with small ceramic output capacitors
that have low ESR and low ESL and are, therefore, easily able to
meet stringent output voltage ripple specifications. X5R or X7R
dielectrics are recommended with a voltage rating of 6.3 V or
10 V. Y5V and Z5U dielectrics are not recommended due to their
poor temperature and dc bias characteristics. The minimum
output capacitance, C
Equation 8.
An acceptable maximum output voltage ripple is
Therefore,
where:
ΔV
ΔI
ESR is the equivalent series resistance of the capacitor in ohms.
f
SW
LOAD_MAX
L
L
RIPPLE
is the converter switching frequency in hertz.
is the peak-to-peak inductor ripple current.
is the inductor ripple current.
For 0.47 μH to 4.7 μH, the TOKO D53LC and
FDV0620 series inductors
For 4.7 μH to 15 μH, the Cooper Bussmann DR1050 series
and the Würth Elektronik WE-PDF series
C
I
ΔV
L
OUT_MIN
_
is the allowable peak-to-peak output voltage ripple in volts.
RIPPLE
PEAK
is the maximum dc load current.
=
≅
≅
I
ΔI
8
LOAD
×
L
×
f
SW
_
⎛
⎜
⎜
⎝
MAX
OUT_MIN
ESR
×
(
ΔV
+
+
RIPPLE
Δ
8
, is determined by Equation 7 and
ΔI
2
×
I
L
L
f
SW
—
ΔI
×
1
C
L
OUT_MIN
×
ESR
)
⎞
⎟
⎟
⎠
L_PEAK
, given by
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(6)
(7)
(8)
If there is a step load, choose the output capacitor value based
on the value of the step load. For the maximum acceptable
output voltage droop/overshoot caused by the step load,
where:
ΔI
f
ΔV
droop/overshoot in volts for the load step.
Note that the previous equations are approximations and are
based on the following assumptions:
•
•
•
Select the largest output capacitance given by Equation 8 and
Equation 9. When choosing the type of ceramic capacitor for
the output filter of the converter, select a capacitor with a nominal
capacitance that is 20% to 30% larger than the calculated value
because the effective capacitance decreases with larger dc voltages.
In addition, the rated voltage of the capacitor must be higher
than the output voltage of the converter.
Recommended input and output ceramic capacitors include
•
•
•
•
•
SW
OUT_STEP
DROOP
is the switching frequency in hertz.
The inductor value is based on the peak-to-peak current
being 30% of the maximum load current.
Voltage drops across the internal MOSFET switches and
across the dc resistance of the inductor are ignored.
In Equation 9, it is assumed that it takes up to three
switching cycles until the loop adjusts the inductor current
in response to the load step.
Murata GRM21BR61A106KE19L, 10 μF, 10 V, X5R, 0805
TDK C2012X5R0J226M, 22 μF, 6.3 V, X5R, 0805
Taiyo Yuden JMK212BJ476MG-T, 47 μF, 6.3 V, X5R, 0805
Murata GRM32ER60J476ME20L, 47 μF, 6.3 V, X5R, 1210
Murata GRM32ER60J107ME20L, 100 μF, 6.3 V, X5R, 1210
C
OUT_MIN
is the maximum allowable output voltage
is the load step value in amperes.
≅
ΔI
OUT_STEP
×
⎛
⎜
⎜
⎝
f
SW
×
ΔV
3
DROOP
⎞
⎟
⎟
⎠
ADP2116
(9)