ADP2116-EVALZ AD [Analog Devices], ADP2116-EVALZ Datasheet - Page 28

• Manufacturer Part Number: ADP2116-EVALZ
• Description: Configurable, Dual 3 A/Single 6 A, Synchronous, Step-Down DC-to-DC Regulator
• Manufacturer: AD [Analog Devices]

ADP2116
CONTROL LOOP COMPENSATION
The ADP2116 uses a peak current-mode control architecture
for excellent load and line transient response. The external
voltage loop is compensated by a transconductance amplifier
with a simple external RC network between the COMP1 or
COMP2 pin and GND, as shown in Figure 69.
The basic control loop block diagram is shown in Figure 70. The
blocks and components shown enclosed within the dashed line in
Figure 70 are embedded inside each channel of the ADP2116.
The control loop can be broken down into the following three
sections:
•
•
•
Correspondingly, there are three transfer functions:
where:
s is the angular frequency that can be written as s = 2πf.
g
G
V
V
Z
Z
m
COMP
FILT
CS
OUT
REF
is the transconductance of the error amplifier, 550 μS.
is the current-sense gain, 4 A/V.
is the internal reference voltage, 0.6 V.
V
V
I
is the impedance of the output filter.
is the output voltage of the converter.
V
V
V
L
V
is the impedance of the RC compensation network.
OUT
COMP
COMP
COMP
OUT
I
to V
OUT
I
C
L
R
L
COMP
(s)
MODULATOR
COMP
(s)
to V
(s)
(s)
to I
(s)
(s)
PULSE-
OUT
WIDTH
Figure 70. Basic Control Loop Block Diagram
=
COMP
L
=
=
Z
V
Figure 69. Compensation Components
V
G
V
FBx
V
ADP2116
COMP
FILT
OUT
CS
REF
0.6V
(s)
g m
×
INDUCTOR
CURRENT
SENSE
g m
g
m
×
Z
V
COMP
REF
C
COMPx
GND
R
COMP
COMP
= 0.6V
(s)
V
ADP2116
IN
I
L
C
C2
V
OUT
(10)
(11)
(12)
Rev. 0 | Page 28 of 36
Z
forms a pole at origin and a zero as expressed in Equation 13.
Z
where s is the angular frequency that can be written as s = 2πf.
The overall loop gain, H(s), is obtained by multiplying the three
transfer functions previously mentioned as follows:
When the switching frequency (f
inductor (L), and output capacitor (C
the unity crossover frequency of approximately 1/12 the
switching frequency can be targeted.
At the crossover frequency, the gain of the open-loop transfer
function is unity. This yields Equation 16 for the compensation
network impedance at the crossover frequency.
To ensure that there is sufficient phase margin at the crossover
frequency, set the compensator zero to 1/8 of the crossover
frequency, as indicated in Equation 17.
Solving Equation 16 and Equation 17 yields the values for the
compensation resistor and the compensation capacitor, as shown
in Equation 18 and Equation 19.
Capacitor C
compensation resistor, R
that the loop gain continues to decrease, or roll off, well beyond
the unity-gain crossover frequency. The value of C
typically set to 1/40 of the compensation capacitor, C
COMP
FILT
( s ) is the impedance of the output filter and is expressed as
H(s) = g
C
Z
Z
Z
R
(s) is the impedance of the RC compensation network that
f
ZERO
COMP
FILT
COMP
COMP
COMP
(s)
(s)
=
(
=
C2
=
f
m
=
2
CROSS
=
0
2
(as shown in Figure 69) forms a pole with the
× G
×
1
9 .
×
1
+
π
×
π
+
CS
)
×
s
⎛
⎜
⎜
⎝
×
s
×
=
R
×
2 (
×
R
f
COMP
R
2
s
ZERO
) π
g
R
LOAD
V
V
×
LOAD
×
1
1
m
COMP
OUT
COMP
REF
C
π
f
G
CROSS
×
COMP
×
×
CS
×
g
C
R
f
m
, in the feedback loop to ensure
×
C
× Z
CROSS
COMP
COMP
×
C
OUT
SW
⎞
× ⎟ ⎟
⎠
COMP
G
COMP
), output voltage (V
CS
⎛
⎜
⎜
⎝
×
≈
C
C
(s) × Z
OUT
OUT
OUT
f
CROSS
V
8
) values are selected,
REF
V
×
OUT
FILT
V
V
OUT
REF
(s)
⎞
⎟
⎟
⎠
C2
OUT
, if used, is
COMP
), output
.
(13)
(14)
(15)
(16)
(17)
(18)
(19)