ADP2116-EVALZ AD [Analog Devices], ADP2116-EVALZ Datasheet - Page 31

• Manufacturer Part Number: ADP2116-EVALZ
• Description: Configurable, Dual 3 A/Single 6 A, Synchronous, Step-Down DC-to-DC Regulator
• Manufacturer: AD [Analog Devices]

5.
Table 11. Channel 2 Circuit Settings
Circuit Parameter
Output Voltage, V
Reference Voltage, V
Error Amplifier Transconductance, g
Current-Sense Gain, G
Switching Frequency, f
Crossover Frequency, f
Zero Frequency, f
Output Inductor, L
Output Capacitor, C
Compensation Resistor, R
Compensation Capacitor, C
Table 12. Selection Table of L, C
f
300
300
300
300
600
600
600
600
600
1200
1200
1200
1200
1200
1
SW
A maximum load of 6.0 A is available only with the single interleaved, dual-phase, 6 A output configuration (see
(kHz)
Calculate the compensation component values of the
feedback loop by using the following equation:
where:
g
G
V
V
C
account for dc bias).
From Equation 18,
Substituting R
m
OUT
CS
REF
OUT
= 550 μS.
= 4 A/V.
= 0.6 V.
R
= 0.8 × (47 + 100) μF (capacitance derated by 20% to
= 1.2 V.
R
COMP
COMP
V
5
5
5
5
5
5
5
5
5
5
5
5
5
5
IN
= 30 kΩ.
ZERO
OUT
(V)
=
OUT
OUT
0
COMP
REF
9 .
CS
SW
CROSS
×
in Equation 19 yields C
COMP
⎛
⎜
⎜
⎝
2 (
COMP
) π
g
m
f
V
3.3
2.5
1.8
1.2
3.3
2.5
1.8
1.2
1.2
2.5
1.8
1.2
1.2
0.8
G
CROSS
m
OUT
CS
OUT
, and Compensation Values
(V)
Setting
Nominal
Typical
Typical
Typical
See Step 2
1/12 f
1/8 f
Step 3
Step 4
See Equation 18
See Equation 19
⎞
× ⎟ ⎟
⎠
⎛
⎜
⎜
⎝
CROSS
C
SW
OUT
V
REF
V
COMP
OUT
Maximum Load (A)
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
6.0
3.0
3.0
3.0
6.0
3.0
⎞
⎟
⎟
⎠
= 820 pF.
Value
1.2 V
0.6 V
550 μS
4 A/V
600 kHz
50 kHz
6.25 kHz
2.2 μH
(47 + 100) μF
30 kΩ
820 pF
Rev. 0 | Page 31 of 36
1
L (μH)
6.8
5.6
4.7
3.3
3.3
3.3
2.2
2.2
2 × 2.2
1.0
1.0
1.0
2 × 1.0
1.0
SYSTEM CONFIGURATION
Complete the following steps to further configure the ADP2116
for this design example:
1.
2.
3.
A schematic of the ADP2116 as configured in the design example
described in the Design Example section is shown in Figure 71.
Other configurations are shown in Figure 72 to Figure 74. An
application circuit of a single interleaved, dual-phase, 6 A output
is shown in Figure 72. The schematic in Figure 73 depicts an
application circuit with a 3A/2A dual-output load and a 300 kHz
switching frequency, and the schematic of a dual-output converter
that works at 1.2 MHz with an adjustable V
in Figure 74.
Table 12 provides the recommended inductor, output capacitor,
and compensation component values for a set of popular input
and output voltage combinations.
Set the switching frequency (f
by connecting the FREQ pin through an 8.2 kΩ resistor
to GND.
Tie SCFG to VDD and use the CLKOUT signal to
synchronize other converters on the same board with the
ADP2116.
Tie OPCFG through an 82 kΩ resistor to GND for 3 A/3 A
maximum output current operation and to enable pulse
skip mode at light load conditions (see Table 7).
C
100
122 (22 + 100)
147 (47 + 100)
247 (47 + 2 × 100)
47
69 (22 + 47)
100
147 (47 + 100)
294 (2 × 47 + 2 × 100)
47
57 (10 + 47)
69 (22 + 47)
141 (3 × 47)
122 (22 + 100)
OUT
(μF)
Figure 72
).
R
30
27
22
30
33
30
30
30
15
33
33
27
13
33
SW
COMP
) to 600 kHz (see Table 5)
(kΩ)
OUT1
and V
ADP2116
C
1600
1800
2200
1600
750
820
820
820
1600
390
390
470
910
390
OUT2
CO P
M
is shown
(pF)