NCP5331_05 ONSEMI [ON Semiconductor], NCP5331_05 Datasheet - Page 18

• Manufacturer Part Number: NCP5331_05
• Description: Two-Phase PWM Controller with Integrated Gate Drivers
• Manufacturer: ONSEMI [ON Semiconductor]

Overvoltage Protection
overvoltage protection. Overvoltage protection (OVP)
addresses the following five cases (in decreasing level of
difficulty):
upper MOSFET shorts during normal operation. The energy
stored in the output filters of both the ATX supply and the
dc/dc converter must be dissipated very quickly or an
overvoltage condition will occur. When the upper MOSFET
shorts, V
loop control, will within approximately 400 ns, command
the upper MOSFETs (those that aren’t shorted) to turn OFF
and all the lower MOSFETs to turn ON. This will cause two
things to occur: V
current will be drawn from the ATX supply. The current
limit in the ATX supply should become active and the input
voltage to the converter will be removed. Now, when the
input voltage drops below the NCP5331’s UVLO threshold
the lower MOSFETs will be turned OFF. At this point, a fair
amount of the energy in the system will have been
dissipated, however, the converter’s output voltage will
begin to rise again as shown in Figure 20. Even if the lower
MOSFETs are not turned OFF at the UVLO threshold, as
V
fully enhance the devices and the CPU may be damaged.
This case is shown in Figure 21.
gate drive voltage. When V
NCP5331 will activate an external crowbar MOSFET via
NOTE:
Figure 20. Overvoltage Occurs with UVLO Enabled
IN
The NCP5331 provides a comprehensive level of
By far the most difficult overvoltage scenario is when the
The NCP5331 avoids the problems with UVLO and the
1. Normal operation, upper MOSFET shorts
2. Upper MOSFET shorted, turn on the ATX power
3. Normal operation, open the voltage feedback signal
4. Normal operation, ground the voltage feedback
5. Open the voltage feedback signal, apply ATX power
decays, adequate gate drive voltage will not exist to
signal
CORE
Using the lower MOSFETs to prevent overvoltage
is not adequate if the MOSFETs are turned OFF at
the UVLO threshold − V
100 ms.
rises and the error amplifier, due to the closed
CORE
will stop increasing, and a very high
CORE
CORE
reaches 4.0 V within
exceeds 2.05 V, the
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NCP5331
18
the CB
and dissipate the remainder of the energy in the system. The
CB
during UVLO. Also, the CB
adequate gate drive to enhance the lower MOSFET. The
OVP circuits in the NCP5331 are not effected when the ATX
supply current limits and V
Figure 23 document successful operation of the CB
circuitry when an upper MOSFET is shorted during normal
operation with 0 A and 45 A loading.
upper MOSFET is shorted and the ATX power is applied. In
this case, V
MOSFET. When V
CPU (2.2 V) adequate gate drive voltage is not available to
enhance the lower MOSFETs or crowbar device enough to
protect the CPU. A typical “Logic Level” MOSFET will
conduct only 100−300 mA for a gate drive of 2.0−2.5 V
(R
device must be lower than 15 mW during startup to prevent
damage to the CPU. The NCP5331 avoids this problem by
taking advantage of the 5 V
If V
the crowbar device. Most modern MOSFETs will be less
than 10 mW for a V
the NCP5331 preventing V
a shorted upper MOSFET during startup.
high value internal pull−up resistor will cause V
V
pulled higher, the error amplifier will “think” V
high and command a lower and lower duty cycle until
V
the error amplifier would command 100% duty cycle and
V
NOTE:
Figure 21. Overvoltage Occurs with UVLO Disabled
FB
CORE
CORE
The second most difficult overvoltage scenario is when an
If the voltage feedback signal (COREFB+) is broken, a
DS(on)
OUT
IN
) to float higher in voltage. As V
OUT
is less than 5 V
is driven to 0 V. Without the internal pull−up resistor
would be driven very high, damaging the CPU.
circuitry is powered by 5 V
Even if the lower MOSFETs remain ON after
UVLO, there is not enough gate drive voltage to
prevent V
= 6 kW to 25 kW). The R
pin. This additional MOSFET will clamp V
CORE
CORE
is equal to V
IN
GS
SB
reaches the maximum rating for the
greater than 4.5 V. Figure 24 shows
from reaching 4.0 V.
, then 5 V will be used to enhance
SB
CORE
IN
voltage from the ATX supply.
OUT
IN
is removed. Figure 22 and
from exceeding 2.0 V with
due to the shorted upper
pin will always have
SB
DS(on)
and is not disabled
FFB
of the crowbar
(and V
CORE
FFB
FB
is too
CORE
) are
(and
OUT