NCP5331_05 ONSEMI [ON Semiconductor], NCP5331_05 Datasheet - Page 23

• Manufacturer Part Number: NCP5331_05
• Description: Two-Phase PWM Controller with Integrated Gate Drivers
• Manufacturer: ONSEMI [ON Semiconductor]

applications, parasitic inductance and resistance should be
considered when laying out the power, filter and feedback
signal sections of the board. Typically, a multilayer board
with at least one ground plane is recommended. If the layout
is such that high currents can exist in the ground plane
underneath the controller or control circuitry, the ground
plane can be slotted to route the currents away from the
controller. The slots should typically not be placed between
the controller and the output voltage or in the return path of
the gate drive. Additional power and ground planes or
islands can be added as required for a particular layout.
inductance of gate drive traces should be minimized. Gate
drive traces should be kept as short and wide as practical and
should have a return path directly below the gate trace.
connected directly to the load to minimize resistive drops
during heavy loads and inductive drops and ringing during
transients. If required, the planes for the output voltage and
return can be interleaved to minimize inductance between
the filter and load.
Noise pick−up should be avoided wherever possible.
Current feedback traces should be routed away from noisy
areas such as the switch node and gate drive signals. If the
current signals are taken from a location other than directly
at the inductor any additional resistance between the
pick−off point and the inductor appears as part of the
inherent inductor resistances and should be considered in
design calculations. The capacitors for the current feedback
networks should be placed as close to the current sense pins
as practical. After placing the NCP5331 control IC, follow
these guidelines to optimize the layout and routing:
With the fast rise, high output currents of microprocessor
Gate drives experience high di/dt during switching and the
Output filter components should be placed on wide planes
The current sense signals are typically tens of millivolts.
1. Place the 1 mF ceramic power−supply bypass
2. Place the MOSFETs to minimize the length of the
3. Place the components associated with the internal
4. Place the current sense components (R
capacitors close to their associated pins: V
V
Gate traces. Orient the MOSFETs such that the
Drain connections are away from the controller and
the Gate connections are closest to the controller.
error amplifier (R
R
V
C
CS
CCH
DRP
FB
S1
REF
, C
, V
) to minimize the trace lengths to the pins
, V
S2
DRP
pins.
, R
CCL1
Layout Guidelines
and COMP.
S
, C
and V
SA
F1
, C
, C
CCL2
SB
F1
) near the CS1, CS2, and
, C
.
C1
, C
C2
, R
C1
S1
, C
, R
CCL
A1
S2
http://onsemi.com
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NCP5331
23
10. The Gate traces are very noisy. Route these away
11. Gate driver returns, GND1 and GND2, should not
12. Try not to “daisy chain” connections to Ground
13. Use a slot in the ground plane to prevent high
5. Place the frequency setting resistor (R
6. Place the MOSFETs and output inductors to
7. Place the input inductor and input capacitor(s) near
8. Place the output capacitors (electrolytic and
9. The trace from the SWNODEs to the current sense
the R
noise. Route noisy traces, such as the SWNODEs
and GATE traces, away from the R
resistor.
reduce the size of the noisy SWNODEs. However,
there is a trade−off between reducing the size of
the SWNODEs for noise reduction and providing
adequate heat−sinking for the synchronous
MOSFETs.
the Drain of the control (upper) MOSFETs. There
is a trade−off between reducing the size of this
node to save board area and providing adequate
heat−sinking for the control (upper) MOSFETs.
ceramic) close to the processor socket or output
connector.
components (R
this away from more sensitive, low−level traces.
The Ground layer can be used to help isolate this
trace.
from more sensitive, low−level traces. Try to keep
each Gate signal on one layer and insure that there
is an uninterrupted return path directly below the
Gate trace. The Ground layer can be used to help
isolate these traces.
be connected to LGND, but instead directly to the
ground plane.
from one via. Ideally, each connection to Ground
will have its own via located as close to the
component as possible.
currents from flowing beneath the control IC. This
slot should form an “island” for signal ground
under the control IC. “Signal ground” and “power
ground” must be separated. Examples of signal
ground include the capacitors at COMP, CS
and 5V
LGND pin to the controller. Examples of power
ground include the capacitors to V
and V
MOSFETs, and the GND1 and GND2 pins of the
controller.
OSC
CCL2
REF
pin. The R
, the resistors at R
, the Source of the synchronous
S1
, R
S2
OSC
) will be very noisy. Route
pin is very sensitive to
OSC
and I
CCH
OSC
OSC
LIM
and V
pin and
) close to
, and the
REF
CCL1
,