NCP5331_05 ONSEMI [ON Semiconductor], NCP5331_05 Datasheet - Page 9

• Manufacturer Part Number: NCP5331_05
• Description: Two-Phase PWM Controller with Integrated Gate Drivers
• Manufacturer: ONSEMI [ON Semiconductor]

PACKAGE PIN DESCRIPTION
Pin No.
11−15
4, 6
10
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
5
7
8
9
CS1, CS2
VID pins
Symbol
5 V
CB
CS
COMP
LGND
GND2
GND1
V
V
R
−SEN
C
C
5 V
V
V
V
V
PGD
GH2
GH1
GL2
GL1
V
I
CCL2
CCL1
DRP
OSC
CCH
CCL
OVC
PGD
LIM
FFB
FB
REF
OUT
REF
SB
Voltage Feedback Pin. To use Adaptive Voltage Positioning (AVP), set the light load offset voltage
by connecting a resistor between V
the offset. For no adaptive positioning connect V
Current sense output for Adaptive Voltage Positioning (AVP). The offset of this pin above the DAC
voltage is proportional to the output current. Connect a resistor from this pin to V
amount AVP or leave this pin open for no AVP. This pin’s maximum working voltage is 4.1 Vdc.
Return for the internal control circuits and the IC substrate connection.
Current sense inputs. Connect the current sense network for the corresponding phase to each in-
put. The input voltages to these pins must be kept within 125 mV of CS
Reference for both differential current sense amplifiers. To balance input offset voltages between
the inverting and non−inverting inputs of the Current Sense Amplifiers, connect this pin to the output
voltage through a resistor equal to one third of the value of the current sense resistors.
Fast Feedback connection to the PWM comparators and input to the Power Good comparator.
Reference output. Decouple to LGND with 0.1 mF.
A resistor from this pin to ground sets the operating frequency and V
Ground connection for the DAC. Provides remote sensing of ground at the load.
Voltage ID DAC inputs. These pins are internally pulled up and clamped at 2.3 V if left unconnected.
Power for GL2.
Low side driver #2.
Return for driver #2.
High side driver #2.
Power for GH1 and GH2.
Open−collector crowbar output pin. This pin is high impedance when an overvoltage condition is
detected at CS
V
logic on the motherboard to disable the ATX supply via PS
placed upstream to disconnect the input voltage.
High side driver #1.
Return for driver #1.
Low side driver #1.
Power for GL1.
Power for the internal control circuits. UVLO sense for Logic connects to this pin.
A capacitor from this pin to ground sets the time the controller will be in hiccup mode current limit.
This timer is started by the first overcurrent condition (set by the I
age at the V
disable this function and hiccup mode current limit will operate indefinitely.
A capacitor from this pin to ground sets the programmable time between when V
PWRGD threshold and when the open−collector PWRGD pin transitions from a logic Low to a logic
High. The minimum delay is internally set to 200 ms. Connecting this pin to 5 V
programmable timer and the delay will be set to the internal delay.
Power Good output. Open collector output that will transition Low when CS
regulation.
Input power for the CB
should be connected to 5 V
this pin must be connected to the NCP5331 controller’s internal voltage reference (5 V
Sets the threshold for current limit. Connect to reference through a resistive divider. This pin’s maxi-
mum working voltage is 3.0 Vdc.
Output of the error amplifier and input for the PWM comparators.
IN
to GND. To prevent failure of the crowbar device, this pin should be used in conjunction with
CCL
REF
pin must be cycled to reset this fault. Connecting this pin to LGND 200 mV will
. Connect this pin to the gate of a MOSFET or SCR to crowbar either V
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OUT
NCP5331
circuitry. To provide maximum overvoltage protection to the CPU, this pin
SB
from the ATX supply (ATX, pin 9). If the CB
9
FB
and V
Description
CORE
FB
. The resistor and the V
directly to V
ON
and/or a relatively fast fuse should be
CORE
LIM
.
FB
voltage). Once timed out, volt-
REF
bias current.
FB
OUT
.
REF
bias current determine
REF
function is not used,
(V
FB
CORE
CORE
will disable the
to set the
REF
crosses the
) is out of
CORE
, pin 8).
or