HIP6028EVAL1 INTERSIL [Intersil Corporation], HIP6028EVAL1 Datasheet - Page 11

• Manufacturer Part Number: HIP6028EVAL1
• Description: Advanced PWM and Dual Linear Power Control with Integrated ACPI Support Interface
• Manufacturer: INTERSIL [Intersil Corporation]

A multi-layer printed circuit board is recommended. Figure 11
shows the connections of the critical components in the
converter. Note that capacitors C
represent numerous physical capacitors. Dedicate one solid
layer for a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another
solid layer as a power plane and break this plane into
smaller islands of common voltage levels. The power plane
should support the input power and output power nodes.
Use copper filled polygons on the top and bottom circuit
layers for the phase nodes. Use the remaining printed circuit
layers for small signal wiring. The wiring traces from the
control IC to the MOSFET gate and source should be sized
to carry 1A currents. The traces for V
sized for 0.2A. Locate C
PWM Controller Feedback Compensation
Both PWM controllers use voltage-mode control for output
regulation. This section highlights the design consideration
for a voltage-mode controller. Apply the methods and
considerations to both PWM controllers.
Figure 12 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage is
regulated to the reference voltage level. The reference
voltage level is the DAC output voltage for the PWM
controller. The error amplifier output (V
the oscillator (OSC) triangular wave to provide a pulse-width
modulated wave with an amplitude of V
The PWM wave is smoothed by the output filter (L
The modulator transfer function is the small-signal transfer
function of V
gain and the output filter, with a double pole break frequency
at F
simply the input voltage, V
oscillator voltage, V
+5V
+3.3V
V
FIGURE 11. PRINTED CIRCUIT BOARD POWER PLANES AND
OUT2
V
IN
LC
OUT3
IN
and a zero at F
OUT
Q3
ISLANDS
C
C
IN
OUT2
/V
E/A
OSC
+12V
. This function is dominated by a DC
ESR
KEY
OUT2
DRIVE3
VOUT2
VIN2
C
.
2-321
SS
HIP6028
IN
. The DC gain of the modulator is
VCC
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
, divided by the peak-to-peak
C
SS PGND
VCC
close to the HIP6028 IC.
OCSET
PHASE
UGATE
LGATE
GND
IN
and C
OUT2
IN
Q1
Q2
C
E/A
OCSET
at the PHASE node.
OUT
) is compared with
need only be
R
L
CR1
could each
OCSET
C
OUT1
OUT1
O
and C
V
OUT1
O
).
HIP6028
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
internal to the HIP6028 and the impedance networks Z
and Z
a closed loop transfer function with an acceptable 0dB
crossing frequency (f
Phase margin is the difference between the closed loop
phase at f
the compensation network’s poles, zeros and gain to the
components (R1, R2, R3, C1, C2, and C3) in Figure 12.
Use these guidelines for locating the poles and zeros of the
compensation network:
F
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
FIGURE 12. VOLTAGE-MODE BUCK CONVERTER
LC
V
=
OSC
FB
--------------------------------------- -
2
. The goal of the compensation network is to provide
0dB
ND
ST
ND
OSC
ST
L
1
ERROR
COMPENSATION DESIGN
O
and 180 degrees The equations below relate
AMP
Pole at the ESR Zero
Zero Below Filter’s Double Pole (~75% F
Zero at Filter’s Double Pole
Pole at Half the Switching Frequency
HIP6028
V
C
E/A
O
COMP
DETAILED FEEDBACK COMPENSATION
PWM
Z
+
0dB
-
COMP
-
+
FB
C1
REFERENCE
) and adequate phase margin.
REFERENCE
F
C2
ESR
+
-
R2
DRIVER
DRIVER
Z
=
IN
---------------------------------------- -
2
Z
FB
ESR C
FB
V
IN
PHASE
1
C3
(PARASITIC)
Z
R1
L
IN
O
O
ESR
R3
C
V
O
OUT
V
IN
OUT
LC
)