HIP6028EVAL1 INTERSIL [Intersil Corporation], HIP6028EVAL1 Datasheet - Page 8

• Manufacturer Part Number: HIP6028EVAL1
• Description: Advanced PWM and Dual Linear Power Control with Integrated ACPI Support Interface
• Manufacturer: INTERSIL [Intersil Corporation]

over-voltage on the PWM output disables all converters and
drives the FAULT pin to VCC.
Figure 7 shows a simplified schematic of the fault logic. An
over-voltage detected on VSEN1 immediately sets the fault
latch. A sequence of three over-current fault signals also
sets the fault latch. A comparator indicates when C
charged (UP signal), such that an under-voltage event on
either linear output (FB2 or FB3) is ignored until after the
soft-start interval (T4 in Figure 6). At startup, this allows
V
input voltage (+12V
counter and the fault latch. Shutting down VOUT1 and
VOUT3 also resets the counter and latch.
Over-Voltage Protection
During operation, a short on the upper PWM MOSFET (Q1)
causes V
over-voltage threshold of 115% (typical) of DACOUT, the
over-voltage comparator trips to set the fault latch and turns
Q2 on as required in order to regulate V
DACOUT. This blows the input fuse and reduces V
The fault latch raises the FAULT pin close to VCC potential.
A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), V
monitored for voltages exceeding 1.26V. Should VSEN1
exceed this level, the lower MOSFET (Q2) is driven on as
needed to regulate V
Over-Current Protection
All outputs are protected against excessive over-currents.
The PWM controller uses the upper MOSFET’s on-
resistance, r
against shorted outputs. The linear regulator restricts the
current through the integrated power device to 230mA
(typically). The linear regulator and the linear controller
monitor VOUT2 and VSEN3, respectively, for under-voltage
to protect against excessive currents.
LUV
OC1
OV
OUT3
SS
0.15V
FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC
4V
to slew up without generating a fault. Cycling the bias
OUT1
+
-
+
-
DS(ON)
SD1&3
POR
to increase. When the output exceeds the
CURRENT
UP
LATCH
OVER
S
R
IN
to monitor the current for protection
OUT1
Q
on the VCC pin) off then on resets the
2-318
to 1.26V.
R
COUNTER
S
OUT1
INHIBIT
LATCH
FAULT
S
R
OUT1
to 1.15 x
Q
SS
OUT1
is
VCC
is fully
FAULT
.
HIP6028
Figures 8 and 9 illustrate the over-current protection with an
overload on V
current increases through the output inductor (L
time T1, the OVER-CURRENT1 comparator trips when the
voltage across Q1 (I
programmed by R
discharges the soft-start capacitor (C
current sink, and increments the counter. C
T2 and initiates a soft-start cycle with the error amplifiers
clamped by soft-start. With OUT1 still overloaded, the
inductor current increases to trip the over-current
comparator. Again, this inhibits all outputs, but the soft-start
voltage continues increasing to 4V before discharging. The
counter increments to 2. The soft-start cycle repeats at T3
and trips the over-current comparator. The SS pin voltage
increases to 4V at T4 and the counter increments to 3. This
sets the fault latch to disable the converter. The fault is
reported on the FAULT pin.
The linear regulator and linear controller monitor the outputs
for an under-voltage. Should excessive currents cause
VOUT2 or VSEN3 to fall below the linear under-voltage
threshold, the LUV signal sets the over-current latch if C
fully charged. Blanking the LUV signal during the C
interval allows the linear outputs to build above the under-
voltage threshold during normal start-up. Cycling the bias
input power off then on resets the counter and the fault latch.
Resistor R
PWM converter. As shown in Figure 9, the internal 200 A
current sink develops a voltage across R
is referenced to V
current comparator (OVER-CURRENT1). When the voltage
across the upper MOSFET (V
over-current comparator trips to set the over-current latch.
Both V
capacitor across R
10V
0A
4V
2V
0V
0V
SET
FIGURE 8. OVER-CURRENT OPERATION
OCSET
T0
and V
COUNT
OUT1
= 1
T1
OVERLOAD
APPLIED
DS
IN
programs the over-current trip level for the
OCSET
OCSET
. The overload is applied at T0 and the
. The DRIVE signal enables the over-
D
are referenced to V
• r
T2
DS(ON)
. This inhibits all outputs,
helps V
COUNT
DS(ON)
TIME
= 2
) exceeds the level
REPORTED
OCSET
FAULT
) exceeds V
SS
) with an 11 A
IN
OCSET
track the variations
T3
and a small
SS
recharges at
COUNT
OUT1
(V
SET
= 3
T4
SS
SET
, the
). At
charge
) that
SS
is