SLB128B NSC [National Semiconductor], SLB128B Datasheet

SLB128B

Manufacturer Part Number

SLB128B

Description

Transmitter with built-in scaler for LVDS Display Interface (LDI)

Manufacturer

NSC [National Semiconductor]

Datasheet

1.SLB128B.pdf (48 pages)

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DS90C2501

Transmitter with built-in scaler for LVDS Display

Interface (LDI)

General Description

The DS90C2501 is a highly integrated scaling IC with LVDS

transmitter with a scaled resolution up to SXGA+ for single

pixel input. The DS90C2501 is a video controller hub de-

signed to be compatible with Graphic Memory Controller

Hub (GMCH). The input interface can be single or dual DVO

port (12 pin per port). The high quality cubic zoom engine

scales the input graphics into the desired/optimal output

resolution up to 1400x1050 resolution. Advanced video digi-

tal signal processing provides gamma correction, and dith-

ering for the display output. A two-wire serial interface is

used to communicate with the host system. The dual high

speed LVDS channels supports single pixel in-single pixel

out, single pixel in-dual pixel out, and dual pixel in-dual pixel

out transmission modes. The DS90C2501 complies to Open

LDI standard, and can be paired up with DS90CF388 re-

ceiver or FPD8531x/FPD8731x series integrated timing con-

troller or FPDLink LVDS receivers such as DS90CF364/

DS90CF384A/DS90CF384/DS90CF384A. The LVDS output

is similar to DS90C387 and DS90C387R. Thus, this trans-

mitter can be paired up with DS90CF388, receiver of

112MHz LDI chipset or FPD-Link Receivers in non-DC Bal-

ance mode operation which provides GUI/LCD panel/mother

board vendors a wide choice of inter-operation with LVDS

based TFT panels.

This chip is an ideal solution to solve EMI and cable size

problems for high-resolution flat panel applications. It pro-

vides a reliable industry standard interface based on LVDS

technology that delivers the bandwidth needed for high-

resolution panels while maximizing bit times, and keeping

clock rates low to reduce EMI and shielding requirements.

For more details, please refer to the “Applications Informa-

tion” section of this datasheet.

TRI-STATE

DVO is a registered trademark of Intel Corporation.

AGP or 4x AGP is a registered trademark of Intel Corporation.

is a registered trademark of National Semiconductor Corporation.

DS200045

Features

n Complies with Open LDI and GMCH DVO specification

n 25 to 65 MHz clock in single pixel in to single pixel out

n 50 to 130 MHz clock in single pixel in to dual pixel out

n Support 24bit/48bit color TFT LCD with Conventional

n Support 16bit/32bit color TFT LCD.

n Single pixel transmitter inputs support single pixel GUI

n Up scaling/panel fitting supports VGA to SXGA+ output

n Independent horizontal and vertical scaling.

n Support dithering (available for 6-bit color only),

n Programmable digital sharpness, edge enhancement

n Allow 2% at 200KHz spread spectrum clocking, rejects

n Programmable LCD panel power sequencing.

n Support low voltage swing signal level (1V to 1.8V),

n Support 2.5V/3.3V LVTTL level on configuration pins

n Support 3.3V LVTTL level on GPIO pins

n Available in 10mm x 10mm x 1mm 128pin thermally

n Two-wire serial communication interface is active during

n TIA/EIA-644, Open LDI, DVO compliance.

for digital display interfaces

operation.

and Non-Conventional Color Mappings.

interface.

in single pixel input mode at 640x480

800x600

1400x1050

programmable smoothing and anti-aliasing filter.

and contrast control via gamma correction.

cycle-to-cycle jitter (+/− 20% of input data bit time).

2.5V and 3.3V LVTTL level on CLKINP, CLKINM, D0 to

D23, DE, HSYNC and VSYNC pins

enhanced CSP package.

normal as well as power down mode and support data

rates up to 400KHz.

60Hz, 1024x768

60Hz.

60Hz, 1280x1024

60Hz,

October 2003

www.national.com

60Hz,

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