SLB128B NSC [National Semiconductor], SLB128B Datasheet - Page 32

• Manufacturer Part Number: SLB128B
• Description: Transmitter with built-in scaler for LVDS Display Interface (LDI)
• Manufacturer: NSC [National Semiconductor]

www.national.com
LVDS Interface
Note 12: The lower half of the pixel is latched by the primary clock edge E1.
Note 13: E3 and E4 only apply when DUAL pin = 1/2 V
Note 14: Above figure only valid when R_FDE bit = V
Note 15: D0 to D11 are clocked at the crossing point of CLKOUT+ and CLKOUT− when differential clock input is applied. This applies to D12 to D23 when DUAL
pin = V
Note 16: Single-ended clock is not recommended for operation above 65MHz by GMCH vendor.
Note 17: Color notation: R = RED, G = GREEN, B = BLUE.
Note 18: Bit significance within a color: [7:0] = [MSB:LSB].
CC
.
Pin Name
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TABLE 9. 12-bit (two data per clock) input application data mapping with GMCH.
(Continued)
G0[3]
G0[2]
G0[1]
G0[0]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
P0L
Low
FIGURE 14. How Data is Latched in the DS90C2501
P0
CC
CC
, DE signal from GUI is set to be active HIGH.
.
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[7]
G0[6]
G0[5]
G0[4]
High
P0H
G1[3]
G1[2]
G1[1]
G1[0]
32
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
Low
P1L
P1
G1[7]
G1[6]
G1[5]
G1[4]
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
High
P1H
G2[3]
G2[2]
G2[1]
G2[0]
B2[7]
B2[6]
B2[5]
B2[4]
B2[3]
B2[2]
B2[1]
B2[0]
Low
P2L
20004533
P2
G2[7]
G2[6]
G2[5]
G2[4]
R2[7]
R2[6]
R2[5]
R2[4]
R2[3]
R2[2]
R2[1]
R2[0]
High
P2H