DSPIC30F2010 MICROCHIP [Microchip Technology], DSPIC30F2010 Datasheet - Page 197

• Manufacturer Part Number: DSPIC30F2010
• Description: High-Performance, 16-Bit Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

Timer2 and Timer3 Selection Mode .................................... 72
Timer2/3 Module ................................................................. 61
TimerQ (QEI Module) External Clock Timing
Timing Characteristics
Timing Diagrams
Timing Diagrams and Specifications
Timing Diagrams.See Timing Characteristics
© 2006 Microchip Technology Inc.
32-bit Synchronous Counter Mode ............................. 61
32-bit Timer Mode....................................................... 61
ADC Event Trigger...................................................... 64
Gate Operation ........................................................... 64
Interrupt....................................................................... 64
Operation During Sleep Mode .................................... 64
Register Map............................................................... 65
Timer Prescaler........................................................... 64
Characteristics .......................................................... 167
A/D Conversion
Band Gap Start-up Time ........................................... 164
CLKO and I/O ........................................................... 161
External Clock........................................................... 157
I
I
Input Capture (CAPx)................................................ 168
Motor Control PWM Module...................................... 170
Motor Control PWM Module Falult............................ 170
OC/PWM Module ...................................................... 169
Oscillator Start-up Timer ........................................... 162
Output Compare Module........................................... 168
Power-up Timer ........................................................ 162
QEI Module Index Pulse ........................................... 172
Reset......................................................................... 162
SPI Module
TimerQ (QEI Module) External Clock ....................... 167
Type A and B Timer External Clock.......................... 165
Watchdog Timer........................................................ 162
Center-Aligned PWM .................................................. 85
Dead-Time .................................................................. 87
Edge-Aligned PWM..................................................... 85
PWM Output ............................................................... 73
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
DC Characteristics - Internal RC Accuracy............... 160
2
2
C Bus Data
C Bus Start/Stop Bits
10-Bit High-speed (CHPS = 01, SIMSAM = 0,
10-bit High-speed (CHPS = 01, SIMSAM = 0,
Master Mode ..................................................... 178
Slave Mode ....................................................... 180
Master Mode ..................................................... 178
Slave Mode ....................................................... 180
Master Mode (CKE = 0) .................................... 173
Master Mode (CKE = 1) .................................... 174
Slave Mode (CKE = 0) ...................................... 175
Slave Mode (CKE = 1) ...................................... 176
Not Tied to V
Not Tied to V
Tied to V
ASAM = 0, SSRC = 000) .......................... 184
ASAM = 1, SSRC = 111, SAMC = 00001) 185
DD
) ...................................................... 130
DD
DD
), Case 1 .................................. 130
), Case 2 .................................. 130
Timing Requirements
Timing Specifications
U
UART
Unit ID Locations .............................................................. 123
Universal Asynchronous Receiver Transmitter. See UART.
A/D Conversion
Band Gap Start-up Time........................................... 164
Brown-out Reset....................................................... 163
CLKO and I/O ........................................................... 161
External Clock .......................................................... 158
I
I
Input Capture............................................................ 168
Motor Control PWM Module ..................................... 170
Oscillator Start-up Timer........................................... 163
Output Compare Module .......................................... 168
Power-up Timer ........................................................ 163
QEI Module
Quadrature Decoder................................................. 171
Reset ........................................................................ 163
Simple OC/PWM Mode ............................................ 169
SPI Module
Type A Timer External Clock .................................... 165
Type B Timer External Clock .................................... 166
Type C Timer External Clock.................................... 166
Watchdog Timer ....................................................... 163
PLL Clock ................................................................. 159
Address Detect Mode ............................................... 107
Auto Baud Support ................................................... 107
Baud Rate Generator ............................................... 107
Enabling and Setting Up UART ................................ 105
Loopback Mode ........................................................ 107
Module Overview...................................................... 103
Operation During CPU Sleep and Idle Modes.......... 108
Receiving Data ......................................................... 106
Reception Error Handling ......................................... 106
Transmitting Data ..................................................... 105
UART1 Register Map ............................................... 109
2
2
C Bus Data (Master Mode) .................................... 179
C Bus Data (Slave Mode) ...................................... 181
High-speed ....................................................... 186
External Clock .................................................. 167
Index Pulse....................................................... 172
Master Mode (CKE = 0).................................... 173
Master Mode (CKE = 1).................................... 174
Slave Mode (CKE = 0)...................................... 175
Slave Mode (CKE = 1)...................................... 177
Alternate I/O ..................................................... 105
Disabling........................................................... 105
Enabling ........................................................... 105
Setting Up Data, Parity and Stop Bit
In 8-bit or 9-bit Data Mode................................ 106
Interrupt ............................................................ 106
Receive Buffer (UxRXB)................................... 106
Framing Error (FERR) ...................................... 107
Idle Status ........................................................ 107
Parity Error (PERR) .......................................... 107
Receive Break .................................................. 107
Receive Buffer Overrun Error (OERR Bit) ........ 106
In 8-bit Data Mode ............................................ 105
In 9-bit Data Mode ............................................ 105
Interrupt ............................................................ 106
Transmit Buffer (UxTXB) .................................. 105
Selections................................................. 105
dsPIC30F2010
DS70118G-page 195