AT91SAM7SE256 ATMEL [ATMEL Corporation], AT91SAM7SE256 Datasheet - Page 17

• Manufacturer Part Number: AT91SAM7SE256
• Description: Product Description
• Manufacturer: ATMEL [ATMEL Corporation]

7. Processor and Architecture
7.1
7.2
7.3
6222ES–ATARM–15-Dec-09
ARM7TDMI Processor
Debug and Test Features
Memory Controller
• RISC processor based on ARMv4T Von Neumann architecture
• Two instruction sets
• Three-stage pipeline architecture
• EmbeddedICE
• Debug Unit
• IEEE1149.1 JTAG Boundary-scan on all digital pins
• Programmable Bus Arbiter
• Address decoder provides selection signals for
• Abort Status Registers
• Misalignment Detector
• Remap Command
• 16-area Memory Protection Unit (Internal Memory and peripheral protection only)
– Runs at up to 55 MHz, providing 0.9 MIPS/MHz (core supplied with 1.8V)
– ARM
– Thumb
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Two watchpoint units
– Test access port accessible through a JTAG protocol
– Debug communication channel
– Two-pin UART
– Debug communication channel interrupt handling
– Chip ID Register
– Handles requests from the ARM7TDMI and the Peripheral DMA Controller
– Four internal 1 Mbyte memory areas
– One 256-Mbyte embedded peripheral area
– Eight external 256-Mbyte memory areas
– Source, Type and all parameters of the access leading to an abort are saved
– Facilitates debug by detection of bad pointers
– Alignment checking of all data accesses
– Abort generation in case of misalignment
– Remaps the SRAM in place of the embedded non-volatile memory
– Allows handling of dynamic exception vectors
AT91SAM7SE512/256/32 Preliminary Summary
®
high-performance 32-bit instruction set
®
high code density 16-bit instruction set
™
(Integrated embedded in-circuit emulator)
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