AT91SAM7SE256 ATMEL [ATMEL Corporation], AT91SAM7SE256 Datasheet - Page 46

• Manufacturer Part Number: AT91SAM7SE256
• Description: Product Description
• Manufacturer: ATMEL [ATMEL Corporation]

Revision History
46
Doc. Rev
6222AS
6222BS
6222CS
6222DS
6222ES
6222FS
AT91SAM7SE512/256/32 Preliminary
Comments
First issue
Revised Memories with condensed mapping.
Added Package Outlines and 144-ball LFBGA pin and ordering information.
Section 12. “Ordering Information” on page 45
Section 6.1 ”JTAG Port
tolerant”
Section 7.6 ”SDRAM
INL and DNL updated in
“Features”
Section 7.1 ”ARM7TDMI
Section 7.8 ”Peripheral DMA Controller”
Section 7.5 ”Static Memory
synchronous operations.
Figure 8-1 ”AT91SAM7SE Memory Mapping”
shown with EBI Chip Select 2.
Section 8.1.2.1 ”Flash
Section 6. ”/O Lines
updated
Section 10.11 ”Timer
Features:
“Mode for General Purpose Two-wire UART Serial Communication” added to
Signal Description:
Table 3-1, “Signal Description
System Controller:
Figure 9-1 ”System Controller Block
on page 2, Fully Static Operation; added, up to 55 MHz at 1.8V and 85°C worst case conditions
Considerations”,
Controller”, Mobile SDRAM controller added to SDRAMC features
Counter”, .....the TC has two output compare and one input capture per channel.
Overview”, updated AT91SAM7SE32 ...”reads as 8192 32-bit words.”
Pins”,
Section 10.14 ”Analog-to-Digital Converter”
Processor”, Runs at up to 55 MHz, providing 0.9 MIPS/MHz (core supplied with 1.8V)
Controller”, Multiple device adaptability includes: compliant w/PSRAM in
Section 6.3 ”Reset
List”, AD0-AD3 and AD4-AD7 comments reversed.
Diagram”, ‘periph_nreset’ changed into ‘power_on_reset’ for RTT.
“JTAG Port
PDC priority list added
Compact Flash not shown w/EBI Chip Select 5. Compact Flash is
ordering information code reference changed
Pin”,
Pins”,
Section 6.5 ”SDCK
“Test
Pin”,
“Reset
Pin”,
Pin”, removed statement: “not 5V
“Debug Unit
“ERASE Pin”
(DBGU)”.
descriptions
6222ES–ATARM–15-Dec-09
Change
Request
Ref.
#2709
#3699
#3826
#4005
#3924
#3833
review
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