LPC1113 NXP [NXP Semiconductors], LPC1113 Datasheet - Page 19

• Manufacturer Part Number: LPC1113
• Description: 32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash and 8 kB SRAM
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
LPC1111_12_13_14
Product data sheet
7.10.1 Features
7.11.1 Features
7.11 10-bit ADC
The I
(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
The LPC1111/12/13/14 contains one ADC. It is a single 10-bit successive approximation
ADC with eight channels.
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The I
I
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
The I
10-bit successive approximation ADC.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 V to V
10-bit conversion time  2.44 s (up to 400 kSamples/s).
Burst conversion mode for single or multiple inputs.
Optional conversion on transition of input pin or timer match signal.
Individual result registers for each ADC channel to reduce interrupt overhead.
2
2
C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.
C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line
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2
2
C-interface is a standard I
C-bus can be used for test and diagnostic purposes.
C-bus controller supports multiple address recognition and a bus monitor mode.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 22 June 2011
DD
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2
C-bus compliant interface with open-drain pins. The
32-bit ARM Cortex-M0 microcontroller
2
LPC1111/12/13/14
C is a multi-master bus and can be
© NXP B.V. 2011. All rights reserved.
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