STR910FAZ32H6T STMICROELECTRONICS [STMicroelectronics], STR910FAZ32H6T Datasheet - Page 19

• Manufacturer Part Number: STR910FAZ32H6T
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STR91xFAx32 STR91xFAx42 STR91xFAx44
Table 7.
0 (high priority)
IRQ Channel
hardware
priority
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
VIC IRQ Channels
VIC input
channel
VIC0.10
VIC0.11
VIC0.12
VIC0.13
VIC0.14
VIC0.15
VIC1.10
VIC1.11
VIC1.12
VIC0.0
VIC0.1
VIC0.2
VIC0.3
VIC0.4
VIC0.5
VIC0.6
VIC0.7
VIC0.8
VIC0.9
VIC1.0
VIC1.1
VIC1.2
VIC1.3
VIC1.4
VIC1.5
VIC1.6
VIC1.7
VIC1.8
VIC1.9
Wake-up Group 0
Wake-up Group 1
Wake-up Group 2
CPU Firmware
Ethernet MAC
Wake-Up (all)
BROWNOUT
Logic Block
TIM Timer 0
TIM Timer 1
TIM Timer 2
TIM Timer 3
CPU Core
CPU Core
Watchdog
UART0
UART1
UART2
SSP0
SSP1
CCU
DMA
USB
USB
CAN
ADC
I2C0
I2C1
RTC
IMC
Logic OR of transmit, receive, and error interrupts of I2C channel
Logic OR of transmit, receive, and error interrupts of I2C channel
Logic OR of 8 interrupt sources: RTC, USB Resume, pins P3.2 to
Logic OR of Ethernet MAC interrupts via its own dedicated DMA
Logic OR of ICI0_0, ICI0_1, OCI0_0, OCI0_1, Timer overflow
Logic OR of ICI1_0, ICI1_1, OCI1_0, OCI1_1, Timer overflow
Logic OR of ICI2_0, ICI2_1, OCI2_0, OCI2_1, Timer overflow
Logic OR of ICI3_0, ICI3_1, OCI3_0, OCI3_1, Timer overflow
Logic OR of all 32 inputs of Wake-Up unit (30 pins, RTC, and
Timeout in WDT mode, Terminal Count in Counter Mode
Logic OR of interrupts from each of the 8 individual DMA
Logic OR of Alarm, Tamper, or Periodic Timer interrupts
Logic OR of 8 Induction Motor Control Unit interrupts
Logic OR of all interrupts from Clock Control Unit
Logic OR of all CAN interface interrupt sources
Logic OR of 8 interrupts from pins P5.0 to P5.7
Logic OR of 8 interrupts from pins P6.0 to P6.7
Logic OR of 5 interrupts from UART channel 0
Logic OR of 5 interrupts from UART channel 1
Logic OR of 5 interrupts from UART channel 2
Logic OR of all interrupts from SSP channel 0
Logic OR of all interrupts from SSP channel 1
Logic OR of high priority USB interrupts
Logic OR of low priority USB interrupts
End of AtoD conversion interrupt
Firmware generated interrupt
Debug Transmit Command
Debug Receive Command
LVD warning interrupt
Interrupt Source
USB Resume)
channels
channel.
P3.7
0
1
Functional overview
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