STR910FAZ32H6T STMICROELECTRONICS [STMicroelectronics], STR910FAZ32H6T Datasheet - Page 84

• Manufacturer Part Number: STR910FAZ32H6T
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Electrical characteristics
7.12.4
84/99
I
V
Table 44.
1. The maximum hold time of the START condition has only to be met if the interface does not stretch the low
2. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
3. C
2
DDQ
Symbol
C electrical characteristics
t
t
t
t
t
SU:STO
HD:STA
HD:DAT
SU:STA
SU:DAT
t
period of SCL signal
undefined region of the falling edge of SCL.
t
t
HIGH
LOW
BUF
C
t
b
t
R
F
b
= total capacitance of one bus line in pF
= 2.7 - 3.6V, V
Bus free time between a STOP
and START condition
Hold time START condition.
After this period, the first clock
pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated
START condition
Data hold time
Data set-up time
Rise time of both SDA and SCL
signals
Fall time of both SDA and SCL
signals
Set-up time for STOP condition
Capacitive load for each bus
line
I
2
C electrical characteristics
DD
Parameter
= 1.65 - 2V, T
(2)
(1)
A
= -40 / 85 °C unless otherwise specified.
Min
250
4.7
4.0
4.7
4.0
4.0
4.7
STR91xFAx32 STR91xFAx42 STR91xFAx44
Standard I
0
1000
Max
300
400
2
C
20+0.1C
20+0.1C
Min
100
1.3
1.3
0.6
0.6
0.6
0.6
(3)
(3)
0
Fast I
b
b
2
C
Max
300
300
400
Unit
ms
pF
µs
µs
µs
µs
ns
ns
ns
ns
µs