MCF5481 FREESCALE [Freescale Semiconductor, Inc], MCF5481 Datasheet - Page 11

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MCF5481

Manufacturer Part Number
MCF5481
Description
Microprocessor Electrical Characteristics
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports
either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.
The SDRAM controller uses SSTL2 and SSTL3 I/O drivers. Both SSTL drive modes are programmable
for either Class I or Class II drive strength.
9.1
The following timing numbers indicate when data will be latched or driven onto the external bus, relative
to the memory bus clock, when operating in SDR mode on write cycles and relative to SDR_DQS on read
cycles. The MCF548x SDRAM controller is a DDR controller that has an SDR mode. Because it is
designed to support DDR, a DQS pulse must still be supplied to the MCF548x for each data beat of an
SDR read. The MCF548x accomplishes this by asserting a signal called SDR_DQS during read cycles.
Care must be taken during board design to adhere to the following guidelines and specs with regard to the
SDR_DQS signal and its usage.
Freescale Semiconductor
SDRAM Bus
SDR SDRAM AC Timing Characteristics
FBCSn, BE/BWEn
TSIZ[1:0]
AD[31:Y]
AD[X:0]
CLKIN
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
R/W
ALE
OE
TA
FB1
Figure 8. FlexBus Write Timing
A[31:Y]
FB2
FB6
TSIZ[1:0]
A[X:0]
DATA
FB7
FB3
FB3
SDRAM Bus
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