MCF5481 FREESCALE [Freescale Semiconductor, Inc], MCF5481 Datasheet - Page 12

• Manufacturer Part Number: MCF5481
• Description: Microprocessor Electrical Characteristics
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

SDRAM Bus
12
NOTES:
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8
Symbol
The frequency of operation is either 2x or 4x the CLKIN frequency of operation. The MCF548X supports a single external
reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI, but SDRAM clock
operates at the same frequency as the internal bus clock. Please see the PLL chapter of the MCF548X Specification for
more information on setting the SDRAM clock rate.
SDCLK is one SDRAM clock in (ns).
Pulse width high plus pulse width low cannot exceed min and max clock period.
Pulse width high plus pulse width low cannot exceed min and max clock period.
SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each
data beat.
SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each
data beat.
The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge
does not affect the memory controller.
Since a read cycle in SDR mode still uses the DQS circuit within the MCF548X, it is most critical that the data valid window
be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input
setup spec is just provided as guidance.
SD10
SD11
SD12
SD13
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
Frequency of Operation
Clock Period (t
Clock Skew (t
Pulse Width High (t
Pulse Width Low (t
Address, CKE, CAS, RAS, WE, BA, CS - Output Valid (t
Address, CKE, CAS, RAS, WE, BA, CS - Output Hold (t
SDRDQS Output Valid (t
SDDQS[3:0] input setup relative to SDCLK (t
SDDQS[3:0] input hold relative to SDCLK (t
Data Input Setup relative to SDCLK (reference only) (t
Data Input Hold relative to SDCLK (reference only) (t
Data and Data Mask Output Valid (t
Data and Data Mask Output Hold (t
MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1
SK
CK
)
)
CKL
CKH
Characteristic
)
)
DQSOV
Table 11. SDR Timing Specifications
)
DH
DV
)
)
DQSIH
DQSIS
)
)
DIH
DIS
CMH
CMV
)
)
)
)
0.25 × SDCLK 0.40 × SDCLK
0.25 × SDCLK
Does not apply. 0.5 SDCLK fixed width.
7.52
0.45
0.45
Min
2.0
1.0
1.5
50
0.5 × SDCLK +
0.75 × SDCLK
Self timed
+0.500ns
1.0ns
TBD
Max
0.55
0.55
133
12
Freescale Semiconductor
SDCLK
SDCLK
Unit
Mhz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
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