COP8SBR9 NSC [National Semiconductor], COP8SBR9 Datasheet - Page 16

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COP8SBR9

Manufacturer Part Number
COP8SBR9
Description
8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout
Manufacturer
NSC [National Semiconductor]
Datasheet

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8.0 Electrical Characteristics
AC Electrical Characteristics (−40˚C ≤ T
Output Pulse Width
USART Bit Time when using External
CKX
USART CKX Frequency when being
Driven by Internal Baud Rate Generator
Reset Pulse Width
t
Note 9: Maximum rate of voltage change must be
Note 10: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V
and outputs driven low but not connected to a load.
Note 11: The HALT mode will stop CKI from oscillating. Measurement of I
G0, and G2–G5 programmed as low outputs and not driving a load; all D outputs programmed low and not driving a load; all inputs tied to V
clock monitor and BOR disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.
Note 12: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages
when biased at voltages
must be limited to
Note 13: If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 t
Note 14: Absolute Maximum Ratings should not be exceeded.
Note 15: V
C
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Interrupt Input Low Time
Timer 1 Input High Time
Timer 1 Input Low Time
Timer 2, 3 Input High Time (Note 6)
Timer 2, 3 Input Low Time (Note 6)
Timer 2, 3 Output High Time
Timer 2, 3 Output Low Time
= instruction cycle time.
cc
must be valid and stable before G6 is raised to a high voltage.
<
Parameter
(V
CC
>
+ 7V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients.
V
CC
(the pins do not have source current when biased at a voltage below V
<
0.5 V/ms.
FIGURE 1. MICROWIRE/PLUS Timing
(Continued)
Conditions
DD
HALT is done with device neither sourcing nor sinking current; with L. A. B, C, E, F,
16
A
≤ +125˚C)
periods
6 CKI
Min
150
150
0.5
CC
1
1
1
1
1
). These two pins will not latch up. The voltage at the pins
(Continued)
>
V
CC
Typ
and the pins will have sink current to V
10138905
C
.
Max
2
CC
; A/D converter and
MCLK or t
MCLK or t
Units
MHz
ns
ns
t
t
t
t
C
C
C
C
CC
CC
C
C

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