COP8SBR9 NSC [National Semiconductor], COP8SBR9 Datasheet - Page 34

• Manufacturer Part Number: COP8SBR9
• Description: 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout
• Manufacturer: NSC [National Semiconductor]

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12.0 Timers
The device contains a very versatile set of timers (T0, T1, T2
and T3). Timers T1, T2 and T3 and associated autoreload/
capture registers power up containing random data.
12.1 TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE Timer T0, which is a
16-bit timer. The user cannot read or write to the IDLE Timer
T0, which is a count down timer.
As described in 13.0 Power Saving Features, the clock to the
IDLE Timer depends on which mode the device is in. If the
device is in High Speed mode, the clock to the IDLE Timer is
the instruction cycle clock (one-fifth of the CKI frequency). If
the device is in Dual Clock mode or Low Speed mode, the
clock to the IDLE Timer is the 32 kHz clock. For the remain-
der of this section, the term “selected clock” will refer to the
clock selected by the Power Save mode of the device.
During Dual Clock and Low Speed modes, the divide by 10
that creates the instruction cycle clock is disabled, to mini-
mize power consumption.
In addition to its time base function, the Timer T0 supports
the following functions:
• Exit out of the Idle Mode (See Idle Mode description)
ITSEL2
0
0
0
0
1
1
TABLE 14. Idle Timer Window Length
ITSEL1
0
0
1
1
0
0
ITSEL0
0
1
0
1
0
1
High Speed
16,384 inst.
32,768 inst.
65,536 inst.
FIGURE 15. Functional Block Diagram for Idle Timer T0
4,096 inst.
8,192 inst.
cycles
cycles
cycles
cycles
cycles
Mode
Reserved - Undefined
Idle Timer Period
0.25 seconds
0.5 seconds
Low Speed
Dual Clock
2 seconds
1 second
seconds
Mode
0.125
or
34
• WATCHDOG logic (See WATCHDOG description)
• Start up delay out of the HALT mode
• Start up delay from BOR
Figure 15 is a functional block diagram showing the structure
of the IDLE Timer and its associated interrupt logic.
Bits 11 through 15 of the ITMR register can be selected for
triggering the IDLE Timer interrupt. Each time the selected
bit underflows (every 4k, 8k, 16k, 32k or 64k selected
clocks), the IDLE Timer interrupt pending bit T0PND is set,
thus generating an interrupt (if enabled), and bit 6 of the Port
G data register is reset, thus causing an exit from the IDLE
mode if the device is in that mode.
In order for an interrupt to be generated, the IDLE Timer
interrupt enable bit T0EN must be set, and the GIE (Global
Interrupt Enable) bit must also be set. The T0PND flag and
T0EN bit are bits 5 and 4 of the ICNTRL register, respec-
tively. The interrupt can be used for any purpose. Typically, it
is used to perform a task upon exit from the IDLE mode. For
more information on the IDLE mode, refer to 13.0 Power
Saving Features.
The Idle Timer period is selected by bits 0–2 of the ITMR
register Bit 3 of the ITMR Register is reserved and should
not be used as a software flag. Bits 4 through 7 of the ITMR
Register are used by the dual clock and are described in
13.0 Power Saving Features.
The ITSEL bits of the ITMR register are cleared on Reset
and the Idle Timer period is reset to 4,096 instruction cycles.
12.1.1 ITMR Register
Bits 7–4: Described in 13.0 Power Saving Features.
LSON HSON DCEN
Bit 7
ITSEL2
1
1
Bit 6
ITSEL1
1
1
Bit 5
ITSEL0
CCK
Bit 4
SEL
0
1
10138918
RSVD ITSEL2 ITSEL1 ITSEL0
Bit 3
High Speed
Mode
Reserved - Undefined
Reserved - Undefined
Idle Timer Period
Bit 2
Bit 1
Low Speed
Dual Clock
Mode
or
Bit 0