COP8SBR9 NSC [National Semiconductor], COP8SBR9 Datasheet - Page 17

• Manufacturer Part Number: COP8SBR9
• Description: 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout
• Manufacturer: NSC [National Semiconductor]

9.0 Pin Descriptions
The COP8SBR9/SCR9/SDR9 I/O structure enables design-
ers to reconfigure the microcontroller’s I/O functions with a
single instruction. Each individual I/O pin can be indepen-
dently configured as output pin low, output high, input with
high impedance or input with weak pull-up device. A typical
example is the use of I/O pins as the keyboard matrix input
lines. The input lines can be programmed with internal weak
pull-ups so that the input lines read logic high when the keys
are all open. With a key closure, the corresponding input line
will read a logic zero since the weak pull-up can easily be
overdriven. When the key is released, the internal weak
pull-up will pull the input line back to logic high. This elimi-
nates the need for external pull-up resistors. The high cur-
rent options are available for driving LEDs, motors and
speakers. This flexibility helps to ensure a cleaner design,
with less external components and lower costs. Below is the
general description of all available pins.
V
pins must be connected.
Users of the LLP package are cautioned to be aware that the
central metal area and the pin 1 index mark on the bottom of
the package may be connected to GND. See figure below:
CKI is the clock input. This can be connected (in conjunction
with CKO) to an external crystal circuit to form a crystal
oscillator. See Oscillator Description section.
RESET is the master reset input. See Reset description
section.
AV
connected to V
resistor ladder D/A converter used within the A/D converter.
AGND is the ground pin for the A/D converter. It should be
connected to GND externally. This is also the bottom of the
resistor ladder D/A converter used within the A/D converter.
The device contains up to six bidirectional 8-bit I/O ports (A,
B, C, E, G and L) and one 4-bit I/O port (F), where each
individual bit may be independently configured as an input
(Schmitt trigger inputs on ports L and G), output or TRI-
STATE under program control. Three data memory address
locations are allocated for each of these I/O ports. Each I/O
port has three associated 8-bit memory mapped registers,
the CONFIGURATION register, the output DATA register and
the Pin input register. (See the memory map for the various
addresses associated with the I/O ports.) Figure 3 shows the
I/O port configurations. The DATA and CONFIGURATION
registers allow for each port bit to be individually configured
CC
CC
and GND are the power supply pins. All V
is the Analog Supply for A/D converter. It should be
FIGURE 2. LLP Package Bottom View
CC
externally. This is also the top of the
10138970
CC
and GND
17
under software control as shown below:
Port A is an 8-bit I/O port. All A pins have Schmitt triggers on
the inputs. The 44-pin package does not have a full 8-bit port
and contains some unbonded, floating pads internally on the
chip. The binary value read from these bits is undetermined.
The application software should mask out these unknown
bits when reading the Port A register, or use only bit-access
program instructions when accessing Port A. These uncon-
nected bits draw power only when they are addressed (i.e.,
in brief spikes).
Port B is an 8-bit I/O port. All B pins have Schmitt triggers on
the inputs.
Port C is an 8-bit I/O port. The 44-pin device does not offer
Port C. The unavailable pins are not terminated. A read
operation on these unterminated pins will return unpredict-
able values. On this device, the associated Port C Data and
Configuration registers should not be used. All C pins have
Schmitt triggers on the inputs. Port C draws no power when
unbonded.
Port E is an 8-bit I/O Port. The 44-pin device does not offer
Port E. The unavailable pins are not terminated. A read
operation on these unterminated pins will return unpredict-
able values. On this device, the associated Port E Data and
Configuration registers should not be used. All E pins have
Schmitt triggers on the inputs. Port E draws no power when
unbonded.
Port F is a 4-bit I/O Port. All F pins have Schmitt triggers on
the inputs.
The 68-pin package has fewer than eight Port F pins, and
contains unbonded, floating pads internally on the chip. The
binary values read from these bits are undetermined. The
application software should mask out these unknown bits
when reading the Port F register, or use only bit-access
program instructions when accessing Port F. The uncon-
nected bits draw power only when they are addressed (i.e.,
in brief spikes).
Port G is an 8-bit port. Pin G0, G2–G5 are bi-directional I/O
ports. Pin G6 is always a general purpose Hi-Z input. All pins
have Schmitt Triggers on their inputs. Pin G1 serves as the
dedicated WATCHDOG output with weak pull-up if the
WATCHDOG feature is selected by the Option register.
The pin is a general purpose I/O if WATCHDOG feature is
not selected. If WATCHDOG feature is selected, bit 1 of the
Port G configuration and data register does not have any
effect on Pin G1 setup. G7 serves as the dedicated output
pin for the CKO clock output.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin, the associated bits in the data and configu-
ration registers for G6 and G7 are used for special purpose
functions as outlined below. Reading the G6 and G7 data
bits will return zeros.
The device will be placed in the HALT mode by writing a “1”
to bit 7 of the Port G Data Register. Similarly the device will
be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
CONFIGURATION
Register
0
0
1
1
Register
DATA
0
1
0
1
Hi-Z Input
(TRI-STATE Output)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output
Port Set-Up
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