MC9S12E128 MOTOROLA [Motorola, Inc], MC9S12E128 Datasheet - Page 134

• Manufacturer Part Number: MC9S12E128
• Description: MC9S12E-Family Device User Guide V01.04
• Manufacturer: MOTOROLA [Motorola, Inc]

Device User Guide — 9S12E128DGV1/D V01.04
In Table B-8 the timing characteristics for master mode are listed.
134
Num
(CPOL = 0)
(CPOL = 1)
10
12
13
11
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
1
1
2
3
4
5
6
9
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
(INPUT)
MISO
MOSI
SCK
SCK
SS
1
C
P
P
D
D
D
D
D
D
D
D
D
D
PORT DATA
SCK Frequency
SCK Period
Enable Lead Time
Enable Lag Time
Clock (SCK) High or Low Time
Data Setup Time (Inputs)
Data Hold Time (Inputs)
Data Valid after SCK Edge
Data Valid after SS fall (CPHA=0)
Data Hold Time (Outputs)
Rise and Fall Time Inputs
Rise and Fall Time Outputs
9
Table B-8 SPI Master Mode Timing Characteristics
2
Characteristic
4
MASTER MSB OUT
5
MSB IN
Figure B-5 SPI Master Timing (CPHA=1)
Freescale Semiconductor, Inc.
1
For More Information On This Product,
6
2
4
Go to: www.freescale.com
2
12
12
11
BIT 6 . . . 1
BIT 6 . . . 1
Symbol
t
t
t
f
t
wsck
t
t
vsck
lead
t
t
t
sck
sck
t
vss
t
lag
ho
rfo
su
hi
rfi
1/2048
Min
20
—
—
—
—
—
—
—
2
8
8
13
13
MASTER LSB OUT
LSB IN
Typ
1/2
1/2
1/2
—
—
—
—
—
—
—
—
—
3
Max
2048
1/2
30
15
—
—
—
—
—
—
8
8
PORT DATA
Unit
f
t
t
t
t
bus
bus
ns
ns
ns
ns
ns
ns
ns
sck
sck
sck