SAH-C515 SIEMENS [Siemens Semiconductor Group], SAH-C515 Datasheet - Page 130

• Manufacturer Part Number: SAH-C515
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

8.1.3 Refreshing the Watchdog Timer
Once started, the watchdog timer can only be cleared to 0000 H by first setting bit WDT and with the
next instruction setting bit SWDT. Bit WDT will automatically be cleared during the second machine
cycle after having been set. For this reason, setting SWDT bit has to be a one cycle instruction (e.g.
SETB SWDT). This double instruction clearing of the watchdog timer was implemented to minimize
the chance of unintentionally clearing the watchdog. To prevent the watchdog from overflowing, it
must be cleared periodically.
Setting only bit SWDT does not reload the watchdog timer automatically to 0000 H . A watchdog
timer reset operation occurs only by using the double instruction refresh sequence SETB WDT /
SETB SWDT.
8.1.4 Watchdog Reset and Watchdog Status Flag
lf the software fails to clear the watchdog in time, an internally generated watchdog reset is entered
at the counter state FFFC H and lasts four instruction cycles. This internal reset differs from an
external reset only to the extent that the watchdog timer is not disabled. Bit WDTS allows the
software to examine from which source the reset was initiated. lf it is set, the reset was caused by
a watchdog timer overflow.
Figure 8-1 shows a block diagram of the watchdog timer.
Figure 8-1
Block Diagram of the Watchdog Timer
Semiconductor Group
f
WDT Reset if WDT count is between
External HW Reset
PE/SWD
OSC
-
-
-
WDTS
SWDT
WDT
-
-
-
÷ 12
Control Logic
-
-
-
-
-
-
-
-
-
FFFC H
8-2
-
-
-
IP0 ( A9 H )
-
FFFF
-
-
-
H
IEN0
IEN1
16-Bit Watchdog Timer
(
( B8 H
A8
H
)
)
Fail Safe Mechanisms
Reset
MCB03210
C515