SAH-C515 SIEMENS [Siemens Semiconductor Group], SAH-C515 Datasheet - Page 158
![no-image](/images/no-image-200.jpg)
SAH-C515
Manufacturer Part Number
SAH-C515
Description
8-Bit CMOS Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.SAH-C515.pdf
(160 pages)
- Current page: 158 of 160
- Download datasheet (912Kb)
F
G
H
I
Semiconductor Group
F0 . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-7
F1 . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-7
Fail save mechanisms . . . . . . . . . . . 8-1–8-4
Features . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Functional units . . . . . . . . . . . . . . . . . . . 1-1
Fundamental structure . . . . . . . . . . . . . 2-1
GATE . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-17
GF0 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2
GF1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2
Hardware reset . . . . . . . . . . . . . . . . . . . 5-1
I/O ports . . . . . . . . . . . . . . . . . . . . . 6-1–6-13
I2FR . . . . . . . . . . . . . . . . . . . . . . . . . 3-7, 7-7
I3FR . . . . . . . . . . . . . . . . . . . . 3-7, 6-25, 7-7
IADC . . . . . . . . . . . . . . . . . . . 3-7, 6-61, 7-8
IDLE . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2
Idle mode . . . . . . . . . . . . . . . . . . . . . 9-3–9-4
IDLS . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2
IE0 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-6
IE1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-6
IEN0 . . . . . . . . 3-4, 3-5, 3-6, 6-27, 7-4, 8-4
IEN1 . . . . 3-4, 3-5, 3-6, 6-27, 6-61, 7-5, 8-4
IEX2 . . . . . . . . . . . . . . . . . . . . . . . . . 3-7, 7-8
IEX3 . . . . . . . . . . . . . . . . . . . . . . . . . 3-7, 7-8
IEX4 . . . . . . . . . . . . . . . . . . . . . . . . . 3-7, 7-8
IEX5 . . . . . . . . . . . . . . . . . . . . . . . . . 3-7, 7-8
IEX6 . . . . . . . . . . . . . . . . . . . . . 3-7, 7-8, 7-8
INT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
INT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
INT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
INT3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
INT4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
INT5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
INT6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Interrupt system . . . . . . . . . . . . . . . 7-1–7-17
Interrupts
Overlapping of data/program memory 4-3
Program memory access . . . . . . . . . . 4-3
Program/data memory timing . . . . . . 4-2
PSEN signal . . . . . . . . . . . . . . . . . . . . 4-3
Role of P0 and P2 . . . . . . . . . . . . . . . 4-1
Block diagram . . . . . . . . . . . . . . . 7-2–7-3
Enable registers . . . . . . . . . . . . . . 7-4–7-5
11-2
L
M
O
P
IP0 . . . . . . . . . . . . . . . . . 3-5, 3-6, 7-11, 8-4
IP1 . . . . . . . . . . . . . . . . . . . . 3-4, 3-6, 7-11
IRCON . . . . . . . . . 3-4, 3-7, 6-27, 6-61, 7-8
IT0 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-6
IT1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 7-6
Logic symbol . . . . . . . . . . . . . . . . . . . . . .1-3
M0 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-17
M1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 6-17
Memory organization . . . . . . . . . . . 3-1–3-2
MX0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
MX1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
MX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
MX2-0 . . . . . . . . . . . . . . . . . . . . . . . . . .6-59
Oscillator operation . . . . . . . . . . . . . 5-4–5-5
OV . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-7
P . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3, 3-7
P0 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4, 3-6
P1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 3-6
P2 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 3-6
P3 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 3-6
P4 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 3-7
P5 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 3-7
P6 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5, 3-7
Package information (P-LCC-68) . . . .10-17
Package information (P-MQFP-80) . .10-18
Parallel I/O . . . . . . . . . . . . . . . . . . 6-1–6-13
PCON . . . . . . . . . . . . . . . 3-5, 3-6, 6-44, 9-2
PDE . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 9-2
External interrupts . . . . . . . . . . . . . . .7-15
Handling procedure . . . . . . . . . . . . . .7-13
Priority registers . . . . . . . . . . . . . . . .7-11
Priority within level structure . . . . . . .7-12
Request flags . . . . . . . . . . . . . . 7-6–7-10
Response time . . . . . . . . . . . . . . . . .7-17
Sources and vector addresses . . . . .7-14
Data memory . . . . . . . . . . . . . . . . . . . .3-2
General purpose registers . . . . . . . . . .3-2
Memory map . . . . . . . . . . . . . . . . . . . .3-1
Program memory . . . . . . . . . . . . . . . .3-2
External clock source . . . . . . . . . . . . .5-5
On-chip oscillator circuitry . . . . . . . . . .5-5
Recommended oscillator circuit . . . . .5-4
Index
C515
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