HT83003 HOLTEK [Holtek Semiconductor Inc], HT83003 Datasheet - Page 14

• Manufacturer Part Number: HT83003
• Description: Q-Voice
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit ²TO². Whereas in
the HALT mode, the overflow will initialize a ²warm re -
set² only the PC and SP are reset to zero. To clear the
contents of the WDT (including the WDT prescaler),
Power Down - HALT
The HALT mode is initialized by a HALT instruction and
results in the following:
·
·
·
·
·
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a ²warm reset². By examining the TO and PDF
flags, the reason for the chip reset can be determined.
The PDF flag is cleared when the system powers-up or
executes the ²CLR WDT² instruction, and is set when
the ²HALT² instruction is executed. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the PC and SP. The other maintain their original
status.
Rev. 0.10
The system oscillator will be turned off but the WDT
oscillator keeps running (if the WDT oscillator is se-
lected).
The contents of the on chip RAM and registers remain
unchanged.
WDT and WDT prescaler will be cleared and recount
again.
All I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
WS7
¾
¾
¾
¾
¾
¾
¾
¾
WS6
¾
¾
¾
¾
¾
¾
¾
¾
WS5
¾
¾
¾
¾
¾
¾
¾
¾
WS4
¾
¾
¾
¾
¾
¾
¾
¾
Preliminary
Watchdog Timer
WDTS Register
WS3
¾
¾
¾
¾
¾
¾
¾
¾
14
three methods are adopted; external reset (external re-
set (a low level to RES), software instructions, or a
HALT instruction. The software instruction is ²CLR
WDT² and execution of the ²CLR WDT² instruction will
clear the WDT.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by mask option. Awakening from an I/O port
stimulus, the program will resume execution of the next
instruction. If awakening from an interrupt, two se-
quence may occur. If the related interrupt is disabled or
the interrupt is enabled by the stack is full, the program
will resume execution at the next instruction. If the inter-
rupt is enabled and the stack is not full, the regular inter-
rupt response takes place.
Once a wake-up event occurs, it takes 1024 system
clock period to resume normal operation. In other
words, a dummy cycle period will be inserted after a
wake-up. If the wake-up results from an interrupt ac-
knowledge, the actual interrupt subroutine will be de-
layed by one more cycle. If the wake-up results in next
instruction execution, this will be executed immediately
after a dummy period is finished. If an interrupt request
flag is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be dis-
abled. To minimize power consumption, all I/O pins
should be carefully managed before entering the HALT
status.
WS2
0
0
0
0
1
1
1
1
WS1
0
0
1
1
0
0
1
1
WS0
0
1
0
1
0
1
0
1
Division Ratio
August 25, 2003
HT83XXX
1:128
1:16
1:32
1:64
1:1
1:2
1:4
1:8