HT83003 HOLTEK [Holtek Semiconductor Inc], HT83003 Datasheet - Page 15

• Manufacturer Part Number: HT83003
• Description: Q-Voice
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

Reset
There are 3 ways in which a reset can occur:
·
·
·
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re -
set² that resets only the PC and SP, leaving the other cir-
cuits in their original state. Some registers remain un-
changed during any other reset conditions. Most
registers are reset to their ²initial condition² when the re-
set conditions are met. By examining the PDF flag and
TO flag, the program can distinguish between different
²chip resets².
Note: ²u² stands for ²unchanged²
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses after a system
power up or when awakening from a HALT state.
When a system power up occurs, the SST delay is
added during the reset period. But when the reset co-
mes from the RES pin, the SST delay is disabled. Any
wake-up from HALT will enable the SST delay.
Rev. 0.10
TO PDF
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
0
u
0
1
1
0
u
1
u
1
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
WDT time-out during normal operation
WDT wake-up HALT
Reset Timing Chart
Reset Circuit
RESET Conditions
Preliminary
15
The functional unit chip reset status are shown below.
Timer Counter 0/1
The TMR0/TMR1 is internal clock source only, i.e. (TM1,
TM0)=(1,0). There is a 3-bit prescaler (TMRS2, TMRS1,
TMRS0) which defines different division ratio of
TMR0/TMR1¢s clock source.
Note:
PC
Interrupt
Prescaler
WDT
Timer counter
Input/output ports
SP
TMRS2,
TMRS1,
TMRS0
TE
TON
TM0,
TM1
Label
¾
TMR0C/TMR1C bit 3 always write ²0²
TMR0C/TMR1C bit 5 always write ²0²
TMR0C/TMR1C bit 6 always write ²1²
TMR0C/TMR1C bit 7 always write ²0²
Bits
0~2
3
4
5
6
7
TMR0C/TMR1C Register
Reset Configuration
Defines the operating clock source
(TMRS2, TMRS1, TMRS0)
000: clock source/2
001: clock source/4
010: clock source/8
011: clock source/16
100: clock source/32
101: clock source/64
110: clock source/128
111: clock source/256
Defines the TMR0/TMR1 active edge
of timer counter
Enable/disable timer counting
(0=disabled; 1=enabled)
Unused bit, read as ²0²
Defines the operating mode
(TM1, TM0)
000H
Disable
Clear
Clear. After master reset,
WDT begins counting
Off
Input mode
Points to the top of the stack
Function
August 25, 2003
HT83XXX