HT83F10 HOLTEK [Holtek Semiconductor Inc], HT83F10 Datasheet - Page 14

• Manufacturer Part Number: HT83F10
• Description: Flash Type Voice OTP MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

time-out or by executing the CLR WDT or HALT in-
struction. The PDF flag is affected only by executing the
power-up.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering an interrupt sequence or execut-
ing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the subroutine
can corrupt the status register, precautions must be
taken to correctly save it.
Interrupt Control Register - INTC, INTCH
Two 8-bit register, known as the INTC and INTCH regis-
ters, controls the operation of both external and internal
timer interrupts. By setting various bits within these reg-
isters using standard bit manipulation instructions, the
enable/disable function of the external and timer inter-
rupts can be independently controlled. A master inter-
rupt bit within this register, the EMI bit, acts like a global
enable/disable and is used to set all of the interrupt en-
able bits on or off. This bit is cleared when an interrupt
Rev. 1.00
HALT or CLR WDT instruction or during a system
C is set if an operation results in a carry during an ad-
dition operation or if a borrow does not take place dur-
ing a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nib-
ble into the low nibble in subtraction; otherwise AC is
cleared.
Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit,
or vice versa; otherwise OV is cleared.
PDF is cleared by a system power-up or executing the
TO is cleared by a system power-up or executing the
WDT time-out.
CLR WDT instruction. PDF is set by executing the
HALT instruction.
CLR WDT or HALT instruction. TO is set by a
Status Register
14
routine is entered to disable further interrupt and is set
by executing the RETI instruction.
Note: In situations where other interrupts may require
Timer Registers
All devices contain two 8-bit Timers whose associated
registers are known as TMR0 and TMR1 which is the lo-
cation where the associated timer's 8-bit value is lo-
cated. Their associated control registers, known as
TMR0C and TMR1C, contain the setup information for
these timers.
Note that all timer registers can be directly written to in
order to preload their contents with fixed data to allow
different time intervals to be setup.
Input/Output Ports and Control Registers
Within the area of Special Function Registers, the I/O
registers and their associated control registers play a
prominent role. All I/O ports have a designated register
correspondingly labeled as PA, PB etc. These labeled
I/O registers are mapped to specific addresses within
the Data Memory as shown in the Data Memory table,
which are used to transfer the appropriate output or in-
put data on that port. With each I/O port there is an asso-
ciated control register labeled PAC, PBC, etc., also
mapped to specific addresses with the Data Memory.
The control register specifies which pins of that port are
set as inputs and which are set as outputs. To setup a
pin as an input, the corresponding bit of the control reg-
ister must be set high, for an output it must be set low.
During program initialisation, it is important to first setup
the control registers to specify which pins are outputs
and which are inputs before reading data from or writing
data to the I/O ports. One flexible feature of these regis-
ters is the ability to directly program single bits using the
change I/O pins from output to input and vice-versa by
manipulating specific bits of the I/O control registers dur-
ing normal program operation is a useful feature of
these devices.
SET [m].i and CLR [m].i instructions. The ability to
servicing within present interrupt service rou-
tines, the EMI bit can be manually set by the pro-
gram after the present interrupt service routine
has been entered.
HT83FXX
May 12, 2009