X40430 INTERSIL [Intersil Corporation], X40430 Datasheet - Page 3

• Manufacturer Part Number: X40430
• Description: Triple Voltage Monitor with Integrated CPU Supervisor
• Manufacturer: INTERSIL [Intersil Corporation]

PIN DESCRIPTION
PRINCIPLES OF OPERATION
Power-on Reset
Applying power to the X40430, X40431, X40434,
X40435 activates a Power-on Reset Circuit that pulls
the RESET/RESET pins active. This signal provides
several benefits.
– It prevents the system microprocessor from starting
– It prevents the processor from operating prior to sta-
– It allows time for an FPGA to download its configura-
– It prevents communication to the EEPROM, greatly
When V
for t
(X40431, X40435) and RESET (X40430, X40434) pin
allowing the system to begin operation.
Pin
10
11
12
13
14
5
6
7
8
9
to operate with insufficient voltage.
bilization of the oscillator.
tion prior to initialization of the circuit.
reducing the likelihood of data corruption on power-up.
PURST
RESET/
V3MON
RESET
V3FAIL
Name
WDO
SDA
SCL
CC
V
V
MR
WP
SS
CC
(selectable) the circuit releases the RESET
exceeds the device V
Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will re-
main HIGH/LOW until the pin is released and for the t
RESET Output. (X40431, X40435) This open drain pin is an active LOW output which goes LOW when-
ever V
grammed time period (t
t
RESET Output. (X40430, X40434) This pin is an active HIGH CMOS output which goes HIGH when-
ever V
grammed time period (t
t
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a
pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and
followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the
watchdog time out period results in WDO going active.
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
Write Protect. WP HIGH prevents writes to any location in the device (including all the registers). It has
an internal pull down resistor (>10MΩ typical).
V3 Voltage Monitor Input. When the V3MON input is less than the V
This input can monitor an unregulated power supply with an external resistor divider or can monitor a
third power supply with no external components. Connect V3MON to V
V3MON comparator is supplied by the V3MON input.
V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than V
HIGH when V3MON exceeds V
WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
Supply Voltage
PURST
PURST
(Continued)
CC
CC
thereafter.
thereafter.
falls below V
falls below V
3
TRIP1
X40430, X40431, X40434, X40435
TRIP1
TRIP1
PURST
PURST
threshold value
voltage or if manual reset is asserted. This output stays active for the pro-
voltage or if manual reset is asserted. This output stays active for the pro-
) on power-up. It will also stay active until manual reset is released and for
) on power-up. It will also stay active until manual reset is released and for
TRIP3
. There is no power-up reset delay circuitry on this pin.
Function
Figure 1. Connecting a Manual Reset Push-Button
Manual Reset
By connecting a push-button directly from MR to ground,
the designer adds manual system reset capability. The
MR pin is LOW while the push-button is closed and
RESET/RESET pin remains HIGH/LOW until the push-
button is released and for t
PURST
System
Reset
thereafter.
X40430, X40434
RESET
TRIP3
SS
or
voltage, V3FAIL goes LOW.
MR
PURST
V
CC
when not used. The
thereafter.
V
CC
TRIP3
and goes
Manual
Reset
July 29, 2005
FN8251.0