X40430 INTERSIL [Intersil Corporation], X40430 Datasheet - Page 6

• Manufacturer Part Number: X40430
• Description: Triple Voltage Monitor with Integrated CPU Supervisor
• Manufacturer: INTERSIL [Intersil Corporation]

C
Now if the desired V
(actual), then add the difference between V
(desired) – V
desired. This is your new V
applied to VXMON and the whole sequence should be
repeated again (see Figure 5).
C
Now if the V
(desired), perform the reset sequence as described in
the next section. The new V
to VXMON will now be: V
(actual) – V
Note: This operation does not corrupt the memory array.
Setting a Lower V
In order to set V
present value, then V
ing to the procedure described below. Once V
has been “reset”, then V
voltage using the procedure described in “Setting a
Higher V
Resetting the V
To reset a V
age (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
V
by 00h for the Data Byte in order to reset V
STOP bit following a valid write operation initiates the
programming sequence. Pin WDO must then be
brought LOW to complete the operation.
After being reset, the value of V
nal value of 1.7V or lesser.
Notes: 1. This operation does not corrupt the memory array.
Figure 5. Sample V
TRIP1
ASE
ASE
V
Adj.
TRIP1
A
B
, 0Bh for V
2. Set V
TRIPx
V
TRIP2
TRIPX
TRIPx
TRIPX
Voltage”.
CC
TRIPX
or V
TRIPx
(desired)).
≅ 1.5(V2MON or V3MON), when setting
voltage, apply the programming volt-
TRIP2
TRIPx
TRIPx
(actual), is higher than the V
TRIP3
TRIP
V
TRIPX
TRIPx
(actual) to the original V
Adj.
Voltage
TRIP2
, and 0Fh for V
TRIPx
respectively.
Voltage (x = 1, 2, 3)
to a lower voltage than the
V2FAIL
Reset Circuit
must first be “reset” accord-
6
is greater than the V
TRIPX
TRIPX
can be set to the desired
TRIPx
TRIPX
voltage to be applied
(desired) – (V
RESET
becomes a nomi-
X40430, X40431, X40434, X40435
that should be
TRIP3
TRIPx
, followed
TRIPX
TRIPX
TRIPX
TRIPX
TRIPX
. The
TRIPx
1
6
2
7
X4043X
CONTROL REGISTER
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is
removed.
The Control Register is accessed with a special pream-
ble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a byte write
operation directly to the address of the register and only
one data byte is allowed for each register write opera-
tion. Prior to writing to the Control Register, the WEL
and RWEL bits must be set using a two step process,
with the whole sequence requiring 3 steps. See "Writing
to the Control Registers" on page 7.
The user must issue a stop, after sending this byte to
the register, to initiate the nonvolatile cycle that stores
WD1, WD0, PUP1, PUP0, and BP. The X40430,
X40431, X40434, X40435 will not acknowledge any
data bytes written after the first byte is entered.
The state of the Control Register can be read at any
time by performing a random read at address 1FFh,
using the special preamble. Only one byte is read by
each register read operation. The master should
supply a stop condition to be consistent with the bus
protocol.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
13
14
PUP1 WD1 WD0
9
8
7
6
5
Adjust
Run
BP
4
V
P
3
0
SCL
SDA
RWEL WEL PUP0
2
µC
1
July 29, 2005
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