ATA5423_06 ATMEL [ATMEL Corporation], ATA5423_06 Datasheet - Page 29

• Manufacturer Part Number: ATA5423_06
• Description: UHF ASK/FSK Transceiver
• Manufacturer: ATMEL [ATMEL Corporation]

4.1
Figure 4-3.
4.2
4841C–WIRE–05/06
Pin CLK
Basic Clock Cycle of the Digital Circuitry
(Control Register 3)
N_RESET
Clock Timing
CLK_ON
VSOUT
CLK
V
FREQ = FREQ2 + FREQ3
Care must be taken to the harmonics of the CLK output signal f
produced by an microprocessor clocked with it, since these harmonics can disturb the reception
of signals if they get to the RF input. In a single channel system, using FREQ = 3803 to 4053
ensures that the harmonics of this signal do not disturb the receive mode. In a multichannel sys-
tem, the CLK signal can either be not used or carefully laid out on the application PCB. The
supply voltage of the microcontroller must also be carefully blocked in a multichannel system.
Pin CLK is an output to clock a connected microcontroller. The clock frequency f
as follows:
Because the enabling of pin CLK is asynchronous, the first clock cycle may be incomplete. The
signal at CLK output has a nominal 50% duty cycle.
The complete timing of the digital circuitry is derived from one clock. As shown in
on page
a divider.
T
The clock cycle of the bit check and the TX bit rate depends on the selected bit-rate range
(BR_Range) which is defined in control register 6 (see
is defined in control register 4 (see
the following formulas for further reference:
f
f
DCLK
Thres_2
DCLK
CLK
• Timing of the polling circuit including bit check
• TX bit rate
=
= 2.38 V (typ)
=
controls the following application relevant parameters:
f
---------- -
f
---------- -
XTO
27, this clock cycle T
XTO
16
3
V
Thres_1
= 2.3 V (typ)
DCLK
is derived from the crystal oscillator (XTO) in combination with
Table 7-13 on page
40). This clock cycle T
Table 7-20 on page
ATA5423/25/28/29
CLK
as well as to the harmonics
42) and XLim which
XDCLK
CLK
is defined by
is calculated
Figure 4-2
29