ATA5423_06 ATMEL [ATMEL Corporation], ATA5423_06 Datasheet - Page 55

• Manufacturer Part Number: ATA5423_06
• Description: UHF ASK/FSK Transceiver
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 9-2.
4841C–WIRE–05/06
Flow Chart Polling Mode/RX Mode (T_MODE = 1, Transparent Mode Active)
Start-up mode:
NO
Receiving mode:
The incoming data stream is passed via pin SDO_TMDO to the connected
microcontroller. If a bit error occurs, the transceiver is not set back to Start-up
mode.
Output level on Pin RX_ACTIVE -> High
I
S
Sleep mode:
All circuits for analog signal processing are disabled. Only XTO and Polling logic
is enabled.
Output level on pin RX_ACTIVE -> Low; I
T
Bit-check mode:
The incoming data stream is analyzed. If the timing indicates a valid transmitter
signal, the control bits VSOUT_EN, CLK_ON and OPM0 are set to 1 and the
transceiver is set to receiving mode. Otherwise the transceiver is set to Sleep
mode (if OPM0 = 0 and T
Output level on Pin RX_ACTIVE -> High
I
T
S
= I
Sleep
Bit-check
Start-up signal processing:
The signal processing circuit is enabled.
Output level on pin RX_ACTIVE -> High; I
T
= I
Start-up PLL:
The PLL is enabled and locked.
Output level on pin RX_ACTIVE -> High; I
Startup_Sig_Proc
Start RX Mode
RX_X
RX_X
= Sleep × 1024 × T
OPM0 = 1
T
SLEEP
?
?
YES
YES
= 0
Start RX Polling Mode
DCLK
SLEEP
Level on pin CS = Low ?
× X
> 0) or stays in Bit-check mode.
NO
RX data stream
available on pin
Sleep
SDO_TMDO
NO
S
YES
= I
S
S
IDLE_X
= I
= I
Set VSOUT_EN = 1
RX_X
Set CLK_ON = 1
Startup_PLL_X
Set OPM0 = 1
Bit check
OK ?
NO
YES
;T
Startup_PLL
Sleep:
X
T
T
T
T
Sleep
DCLK
Startup_PLL
Startup_Sig_Proc
Bit-check
:
:
:
:
:
Defined by bits Sleep0 to Sleep4 in Control
Register 4
Defined by bit XSleep in Control Register 4
Basic clock cycle
798.5 × T
882 × T
498 × T
306 × T
210 × T
Is defined by the selected bit-rate range and
T
Baud0 and Baud1 in Control Register 6.
If the datastream is interrupted in FSK mode, the
FSK-Demodulator-PLL tends to lock out and is
further not able to lock in, even if there is a valid
data stream available.
In this case, the transceiver must be set back to
IDLE mode.
Depends on the result of the bit check.
If the bit check is ok, T
number of bits to be checked (N
on the utilized data rate.
If the bit check fails, the average time period for
range and on T
defined by bit Baud0 and Baud1 in Control
Register 6.
that check depends on the selected bit-rate
DCLK
. The bit-rate range is defined by bit
DCLK
DCLK
DCLK
DCLK
DCLK
ATA5423/25/28/29
(typ)
XDCLK
(BR_Range 0)
(BR_Range 1)
(BR_Range 2)
(BR_Range 3)
. The bit-rate range is
Bit-check
depends on the
Bit-check
) and
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