ATA5423_06 ATMEL [ATMEL Corporation], ATA5423_06 Datasheet - Page 45
![no-image](/images/no-image-200.jpg)
ATA5423_06
Manufacturer Part Number
ATA5423_06
Description
UHF ASK/FSK Transceiver
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATA5423_06.pdf
(100 pages)
- Current page: 45 of 100
- Download datasheet (2Mb)
Figure 7-3.
4841C–WIRE–05/06
Timing Flow Pin Tn, Status Bit STn
If the transceiver is in any active mode (IDLE, AUX, TX, RX, RX_Polling), an integrated
debounce logic is active. If there is an event on pin Tn a debounce counter is set to 0 (T = 0) and
started. The status is updated, an interrupt is issued and the debounce counter is stopped after
reaching the counter value T = 8195
An event on the same key input before reaching T = 8195
An event on an other key input before reaching T = 8195
debounce counter.
While the debounce counter is running, the bits VSOUT_EN and CLK_ON in control register 3
are set to “1”.
The interrupt is deleted after reading the status register or executing the command Delete_IRQ.
If pin Tn is not used, it can be left open because of an internal pull-up resistor (typically 50 kΩ).
Start debounce counter
Stop debounce counter
RX Polling Mode or
Event on pin Tn ?
IDLE Mode or
AUX Mode or
TX Mode or
Event on pin
Tn = STn ?
RX Mode
T = 0
Tn ?
Y
Y
Y
N
N
N
Stop debounce counter
T = 8195 × T
Pin Tn = 0 ?
STn = 1;
IRQ = 1
?
×
Y
Y
T
DCLK
DCLK
.
N
N
Stop debounce counter
STn = 0;
IRQ = 1
×
T
ATA5423/25/28/29
DCLK
×
T
DCLK
stops the debounce counter.
resets and restarts the
45
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