X5001V8IZ-2.7 INTERSIL [Intersil Corporation], X5001V8IZ-2.7 Datasheet - Page 12

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X5001V8IZ-2.7

Manufacturer Part Number
X5001V8IZ-2.7
Description
CPU Supervisor
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
POWER-UP TIMING
CAPACITANCE (T
Notes: (1) V
EQUIVALENT A.C. LOAD CIRCUIT
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Data Input Timing
Symbol
C
SymboL
Symbol
Output
t
C
t
PUW
OUT
t
PUR
t
t
t
t
WC
f
LEAD
t
IN
t
t
RI
SCK
CYC
LAG
t
FI
t
WH
WL
SU
t
CS
(2) This parameter is periodically sampled and not 100% tested.
H
(2)
(3)
(3)
1.64kΩ
(4)
(2)
(2)
(2)
IL
min. and V
Output capacitance (SO, RESET)
Input capacitance (SCK, SI, CS)
3V
Power-up to read operation
Power-up to write operation
Clock frequency
Cycle time
CS lead time
CS lag time
Clock HIGH time
Clock LOW time
Data setup time
Data hold time
Input rise time
Input fall time
CS deselect time
Write cycle time
1.64kΩ
A
IH
= +25°C, f = 1MHz, V
max. are for reference only and are not tested.
100pF
12
Parameter
Parameter
RESET
Test
CC
5V
= 5V)
3.3kΩ
30pF
X5001
1000
Min.
400
400
400
400
100
100
250
0
1.8V-3.6V
A.C. TEST CONDITIONS
Input pulse levels
Input rise and fall times
Input and output timing level
Min.
Max.
Max.
10
1
2
2
8
6
Min.
500
200
200
200
200
150
50
50
0
Max.
Unit
pF
pF
1
5
2.7V-5.5V
V
10ns
V
CC
CC
Max.
x 0.1 to V
x0.5
10
2
2
2
Conditions
V
V
OUT
IN
Unit
ms
ms
= 0V
= 0V
CC
May 30, 2006
Unit
MHz
ms
FN8125.1
x 0.9
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns

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